Dma mode (dmode), Scratch register a (scratcha), 0x38 – Avago Technologies LSI53C896 User Manual
Page 180: Register: 0x38
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Registers
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Registers: 0x34–0x37
Scratch Register A (SCRATCHA)
Read/Write
SCRATCHA
Scratch Register A
[31:0]
This is a general purpose, user-definable scratch pad
register. Apart from CPU access, only register read/write
and memory moves into the SCRATCH register alter its
contents. The power-up value of this register is
indeterminate.
A special mode of this register is enabled by setting the
PCI Configuration Info Enable bit in the
register. If this bit is set, the
register returns bits
[31:10] of the PCI
Base Address Register One (MEMORY)
in bits [31:10] of the SCRATCH A register when read. Bits
[9:0] of SCRATCH A always return zero in this mode.
Writes to the SCRATCHA register are unaffected. Clearing
the PCI Configuration Info Enable bit causes the
SCRATCH A register to return to normal operation.
Register: 0x38
DMA Mode (DMODE)
Read/Write
BL
Burst Length
[7:6]
These bits control the maximum number of Dwords
transferred per bus ownership, regardless of whether the
transfers are back to back, burst, or a combination of both.
This value is also independent of the width (64 or 32 bits)
of the data transfer on the PCI bus. The LSI53C896 SCSI
function asserts the Bus Request (REQ/) output when the
DMA FIFO can accommodate a transfer of at least one
burst threshold of data. Bus Request (REQ/) is also
31
0
SCRATCHA
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
BL
SIOM
DIOM
ERL
ERMP
BOF
MAN
0
0
0
0
0
0
0
0