Avago Technologies LSI53C896 - Manual (Page 291)

PCI and External Memory Interface Timing Diagrams 6-23
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.17 Nonburst Opcode Fetch, 32-Bit Address and Data
t
7
t
9
t
3
t
4
t
1
t
3
t
1
CLK
(Driven by System)
GPIO0_FETCH/
(Driven by LSI53C896)
GPIO1_MASTER/
(Driven by LSI53C896)
REQ/
(Driven by LSI53C896)
PAR
(Driven by LSI53C896-
IRDY/
(Driven by LSI53C896)
TRDY/
(Driven by Target)
STOP/
(Driven by Target)
DEVSEL/
(Driven by Target)
t
1
t
8
t
6
t
3
AD[31:0]
(Driven by LSI53C896-
C_BE[3:0]/
(Driven by LSI53C896)
t
3
CMD
t
2
REQ64/
(Driven by LSI53C896)
ACK64/
(Driven by LSI53C896)
t
10
t
1
t
2
GNT/
(Driven by Arbiter)
FRAME/
(Driven by LSI53C896)
t
5
Data
In
Addr
Out
Data
In
Addr
Out
Byte
Enable
CMD
Byte
Enable
t
3
t
2
t
2
Addr; Target-Data)
Addr; Target-Data)