Scsi timer zero (stime0), Register: 0x48 – Avago Technologies LSI53C896 User Manual
Page 199
SCSI Registers
4-87
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x48
SCSI Timer Zero (STIME0)
Read/Write
HTH[3:0]
Handshake-to-Handshake Timer Period
[7:4]
These bits select the handshake-to-handshake time-out
period, the maximum time between SCSI handshakes
(SREQ/ to SREQ/ in target mode, or SACK/ to SACK/ in
the initiator mode). When this timing is exceeded, an
interrupt is generated and the HTH bit in the
SCSI Interrupt Status One (SIST1)
register is set. The
following table contains time-out periods for the
Handshake-to-Handshake Timer, the
Selection/Reselection Timer (bits [3:0]), and the General
Purpose Timer (
bits [3:0]).
For a more detailed explanation of interrupts, refer to
Chapter 2, “Functional Description.”
7
4
3
0
HTH[3:0]
SEL[3:0]
0
0
0
0
0
0
0
0
HTH[7:4], SEL[3:0], GEN[3:0]
1
Minimum Time-Out
(40 or 160 MHz)
2
0000
Disabled
0001
125
µ
s
0010
250
µ
s
0011
500
µ
s
0100
1 ms
0101
2 ms
0110
4 ms
0111
8 ms
1000
16 ms
1001
32 ms
1010
64 ms
1011
128 ms
1100
256 ms
1101
512 ms
1110
1.024 s
1111
2.048 s
1. These values are correct if the CCF bits in the
register are set according to
the valid combinations in the bit description.
2. Ultra2 SCSI operation requires a quadrupled 40 MHz clock.