Avago Technologies LSI53C896 User Manual
Page 247
I/O Instructions
5-19
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
register is cleared. When
the carry bit is cleared, the corresponding bit in the ALU
is cleared.
RA
Relative Addressing Mode
26
When this bit is set, the 24-bit signed value in the
register is used as a relative
displacement from the current
address. Use this bit only
in conjunction with the Select, Reselect, Wait Select, and
Wait Reselect instructions. The Select and Reselect
instructions can contain an absolute alternate jump
address or a relative transfer address.
TI
Table Indirect Mode
25
When this bit is set, the 24-bit signed value in the
register is added to the value in
the
register, and used as an
offset relative to the value in the Data Structure Address
(DSA) register. The
value,
SCSI ID, synchronous offset and synchronous period are
loaded from this address. Prior to the start of an I/O, load
the
with the base address
of the I/O data structure. Any address on a Dword
boundary is allowed. After a Table Indirect opcode is
fetched, the
is added to the
24-bit signed offset value from the opcode to generate the
address of the required data. Both positive and negative
offsets are allowed. A subsequent fetch from that address
brings the data values into the chip.
SCRIPTS can directly execute operating system I/O data
structures, saving time at the beginning of an I/O
operation. The I/O data structure can begin on any Dword
boundary and may cross system segment boundaries.
There are two restrictions on the placement of data in
system memory:
•
The I/O data structure must lie within the 8 Mbytes
above or below the base address.
•
An I/O command structure must have all four bytes
contiguous in system memory, as follows. The
offset/period bits are ordered as in the