Avago Technologies LSI53C896 - Manual (Page 130)

4-18 Registers
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Registers: 0x44–0x45
Power Management Control/Status (PMCSR)
Read/Write
PST PME_Status 15
The LSI53C896 always returns a zero for this bit,
indicating that PME signal generation is not supported
from D3cold.
DSCL[1:0] Data_Scale [14:13]
The LSI53C896 does not support the Data register.
Therefore, these two bits are always cleared.
DSLT[3:0] Data_Select [12:9]
The LSI53C896 does not support the data register.
Therefore, these four bits are always cleared.
PEN PME_Enable 8
The LSI53C896 always returns zero for this bit to indicate
that PME assertion is disabled.
R Reserved [7:2]
PWS[1:0] Power State [1:0]
Bits [1:0] determine the current power state of the
LSI53C896. They place the LSI53C896 in a new power
state. Power states are defined as:
Refer to Section 2.5, “Power Management,” for
descriptions of the Power Management States.
15 14 13 12 9 8 7 2 0
PST DSCL[1:0] DSLT[3:0] PEN R PWS[1:0]
0 0 0 0 0 0 0 0 x x x x x x 0 0
0b00 D0
0b01 D1
0b10 D2
0b11 D3 hot