Avago Technologies LSI53C896 - Manual (Page 145)

SCSI Registers 4-33
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x05
SCSI Transfer (SXFER)
Read/Write
Note: When using Table Indirect I/O commands, bits [7:0] of this
register are loaded from the I/O data structure.
TP[2:0] SCSI Synchronous Transfer Period [7:5]
These bits determine the SCSI synchronous transfer
period used by the LSI53C896 SCSI function when
sending synchronous SCSI data in either the initiator or
target mode. These bits control the programmable
dividers in the chip.
The synchronous transfer period the LSI53C896 should
use when transferring SCSI data is determined in the
following example:
The LSI53C896 is connected to a hard disk which can
transfer data at 10 Mbytes/s synchronously. The
LSI53C896 SCSI function’s SCLK is running at 40 MHz.
The synchronous transfer period (SXFERP) is found
as follows:
SXFERP = Period/SSCP + ExtCC
Period = 1
÷
Frequency = 1
÷
10 Mbytes/s = 100 ns
SSCP = 1
÷
SSCF = 1
÷
40 MHz = 25 ns
7 5 4 0
TP[2:0] MO[4:0]
0 0 0 0 0 0 0 0
TP2 TP1 TP0 XFERP
0 0 0 4
0 0 1 5
0 1 0 6
0 1 1 7
1 0 0 8
1 0 1 9
1 1 0 10
1 1 1 11