Avago Technologies LSI53C896 User Manual
Page 231
SCSI SCRIPTS
5-3
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
DMA SCRIPTS Pointer Save (DSPS)
register. The third word, used only
by Memory Move instructions, is loaded into the
shadow register. In an indirect I/O or Move instruction, the first two 32-bit
opcode fetches are followed by one or two more 32-bit fetch cycles.
Sample Operation – The following example describes execution of a
SCRIPTS Block Move instruction.
•
The host CPU, through programmed I/O, gives the
register (in the Operating register file)
the starting address in main memory that points to a SCSI SCRIPTS
program for execution.
•
Loading the
register causes the
LSI53C896 to fetch its first instruction at the address just loaded.
This fetch is from main memory or the internal RAM, depending on
the address.
•
The LSI53C896 typically fetches two Dwords (64 bits) and decodes
the high-order byte of the first Dword as a SCRIPTS instruction. If
the instruction is a Block Move, the lower three bytes of the first
Dword are stored and interpreted as the number of bytes to move.
The second Dword is stored and interpreted as the 32-bit beginning
address in main memory to which the move is directed.
•
For a SCSI send operation, the LSI53C896 waits until there is
enough space in the DMA FIFO to transfer a programmable size
block of data. For a SCSI receive operation, it waits until enough data
is collected in the DMA FIFO for transfer to memory. At this point, the
LSI53C896 requests use of the PCI bus again to transfer the data.
•
When the LSI53C896 is granted the PCI bus, it executes (as a bus
master) a burst transfer (programmable size) of data, decrements the
internally stored remaining byte count, increments the address
pointer, and then releases the PCI bus. The LSI53C896 stays off the
PCI bus until the FIFO can again hold (for a write) or has collected
(for a read) enough data to repeat the process.
The process repeats until the internally stored byte count has reached
zero. The LSI53C896 releases the PCI bus and then performs another
SCRIPTS instruction fetch cycle, using the incremented stored address
maintained in the
register. Execution of
SCRIPTS instructions continues until an error condition occurs or an
interrupt SCRIPTS instruction is received. At this point, the LSI53C896