Avago Technologies LSI53C896 - Manual (Page 356)

IX-6 Index
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
D
D1_Support (D1S) 4-17
D2_Support (D2S) 4-17
data
(DATA) 4-19
acknowledge status (DACK) 4-58
compare mask 5-32
compare value 5-33
parity error reported (DPR) 4-6
paths 2-32
request status (DREQ) 4-58
structure address (DSA) 4-50
transfer direction (DDIR) 4-56
data_scale (DSCL[1:0]) 4-18
data_select (DSLT[3:0]) 4-18
data-in 2-54 , 2-55
data-out 2-54 , 2-55
DC characteristics 6-1
decode of MAD pins 3-23
default download mode 2-57
destination
address 5-24
I/O-memory enable (DIOM) 4-70
detected parity error (from slave) (DPE) 4-5
determining data transfer rate 2-40
device
ID (DID) 4-3
select 3-8
specific initialization (DSI) 4-17
DEVSEL/ 3-8
timing (DT[1:0]) 4-6
diffsens mismatch (DIFF) 4-49
DIP 2-48
direct 5-20
disable
auto FIFO clear (DISFC) 4-102
dual address cycle (DDAC) 4-104
halt on parity error or ATN (target only) (DHP) 4-25
internal load/store (DILS) 4-103
pipe req (DPR) 4-103
single initiator response (DSI) 4-98
disconnect 2-20
disconnect instruction 5-16
DMA
byte counter (DBC) 4-65
command (DCMD) 4-66
control (DCNTL) 2-7 , 2-8 , 2-9 , 2-45 , 4-72
direction (DDIR) 4-63
FIFO 2-9 , 2-31 , 2-44
(DF[7:0]) 4-64
(DFIFO) 4-60
byte offset counter, bits [9:8] (BO[9:8]) 4-64
empty (DFE) 4-42
sections 2-31
size (DFS) 4-63
interrupt 2-45 , 2-46 , 2-48
enable (DIEN) 2-28 , 2-45 , 2-46 , 4-71
interrupt pending (DIP) 4-53
interrupts 2-48
mode (DMODE) 2-7 , 2-8 , 2-9 , 2-12 , 2-25 , 4-68
next address (DNAD) 4-66
next address 64 (DNAD64) 4-110
SCRIPTS
pointer (DSP) 4-67
pointer save (DSPS) 4-67
status (DSTAT) 2-28 , 2-44 , 2-45 , 2-47 , 2-48 , 2-49 , 4-
41
DSA
relative 5-38
relative selector (DRS) 4-109
DSPS register 5-36
dual address cycles 2-22
dynamic block move selector (DBMS) 4-110
E
enable
64-bit
direct BMOV (EN64DBMV) 4-104
table indirect BMOV (EN64TIBMV) 4-104
bus mastering (EBM) 4-4
I/O space (EIS) 4-4
jump on nondata phase mismatches (ENNDJ) 4-102
memory space (EMS) 4-4
parity
checking 2-27
checking (EPC) 4-23
error response (EPER) 4-3
phase mismatch jump (ENPMJ) 4-101
read
line (ERL) 4-70
multiple (ERMP) 4-70
response to
reselection (RRE) 4-32
selection (SRE) 4-32
wide SCSI (EWS) 4-30
enabling cache mode 2-11
encoded
chip SCSI ID (ENC[3:0]) 4-32
destination SCSI ID
(ENC[3:0]) 4-37
(ENID) 4-40
SCSI destination ID 5-21
entry storage address (ESA) 4-114
error reporting signals 3-9