Avago Technologies LSI53C896 User Manual
Page 75
SCSI Functional Description
2-47
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
When the LSI53C896 is initialized, enable all fatal interrupts if hardware
interrupts are being used. If a fatal interrupt is disabled and that interrupt
condition occurs, the SCRIPTS halts and the system never knows it
unless it times out and checks the
Interrupt Status Zero (ISTAT0)
, and
registers after a certain period of inactivity.
If ISTAT is being polled instead of using hardware interrupts, then
masking a fatal interrupt makes no difference because the SIP and DIP
bits in the
Interrupt Status Zero (ISTAT0)
inform the system of interrupts,
not the INTA/ (or INTB/) pin.
Masking an interrupt after INTA/ (or INTB/) is asserted does not cause
deassertion of INTA/ (or INTB/).
2.2.17.5 Stacked Interrupts
The LSI53C896 stacks interrupts, if they occur, one after the other. If the
SIP or DIP bits in the
Interrupt Status Zero (ISTAT0)
register are set (first
level), then there is already at least one pending interrupt, and any future
interrupts are stacked in extra registers behind the
SCSI Interrupt Status Zero (SIST0)
SCSI Interrupt Status One (SIST1)
,
and
registers (second level). When two interrupts
have occurred and the two levels of the stack are full, any further
interrupts set additional bits in the extra registers behind SIST0, SIST1,
and DSTAT. When the first level of interrupts are cleared, all the
interrupts that came in afterward move into SIST0, SIST1, and DSTAT.
After the first interrupt is cleared by reading the appropriate register, the
INTA/ (or INTB/) pin is deasserted for a minimum of three CLKs; the
stacked interrupts move into SIST0, SIST1, or DSTAT; and the INTA/
(or INTB/) pin is asserted again.
Because a masked nonfatal interrupt does not set the SIP or DIP bits,
interrupt stacking does not occur. A masked, nonfatal interrupt still posts
the interrupt in
SCSI Interrupt Status Zero (SIST0)
, but does not assert
the INTA/ (or INTB/) pin. Because no interrupt is generated, future
interrupts move into SIST0 or
SCSI Interrupt Status One (SIST1)
instead
of being stacked behind another interrupt. When another condition
occurs that generates an interrupt, the bit corresponding to the earlier
masked nonfatal interrupt is still set.