Avago Technologies LSI53C896 - Manual (Page 321)

PCI and External Memory Interface Timing Diagrams 6-53
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.30 Normal/Fast Memory (
≥
128 Kbytes) Multiple Byte Access Write Cycle (Cont.)
CLK
(Driven by System)
PAR
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C896)
STOP/
(Driven by LSI53C896)
DEVSEL/
(Driven by LSI53C896)
AD[31:0]
C_BE[3:0]/
(Driven by Master)
FRAME/
(Driven by Master)
MAD
(Driven by LSI53C896)
MAS1/
(Driven by LSI53C896)
MAS0/
(Driven by LSI53C896)
MCE/
(Driven by LSI53C896)
MOE/
(Driven by LSI53C896)
MWE/
(Driven by LSI53C896)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Byte Enable
16 32 33
Low Order
Address
Data In
Data Out
(Driven by Master)
(Driven by Master)