Avago Technologies LSI53C896 - Manual (Page 118)

4-6 Registers
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
DT[1:0] DEVSEL/ Timing [10:9]
These bits encode the timing of DEVSEL/. These are
encoded as:
These bits are read only and should indicate the slowest
time that a device asserts DEVSEL/ for any bus command
except Configuration Read and Configuration Write. The
LSI53C896 supports a value of 0b01.
DPR Data Parity Error Reported 8
This bit is set when the following conditions are met:
•
The bus agent asserted PERR/ itself or observed
PERR/ asserted and;
•
The agent setting this bit acted as the bus master for
the operation in which the error occurred and;
•
The Parity Error Response bit in the Command
register is set.
R Reserved [7:5]
NC New Capabilities 4
This bit is set to indicate a list of extended capabilities
such as PCI Power Management. This bit is read only.
R Reserved [3:0]
Register: 0x08
Revision ID (Rev ID)
Read Only
RID Revision ID [7:0]
This register specifies a device specific revision identifier.
The upper nibble is always set to 0x0000. The lower
nibble reflects the current revision level of the device.
0b00 fast
0b01 medium
0b10 slow
0b11 reserved
7 0
RID
0 0 0 0 x x x x