Avago Technologies LSI53C896 User Manual
Page 72
2-44
Functional Description
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Refer to Register 0x14,
Interrupt Status Zero (ISTAT0)
, Bit 5 signal
process in
for details.
The host (C Code) or the SCRIPTS code could potentially try to access
the mailbox bits at the same time.
If the SIP bit in the
Interrupt Status Zero (ISTAT0)
register is set, then a
SCSI-type interrupt has occurred and the
SCSI Interrupt Status Zero (SIST0)
and
SCSI Interrupt Status One (SIST1)
registers should be read.
If the DIP bit in the
Interrupt Status Zero (ISTAT0)
register is set, then a
DMA-type interrupt has occurred and the
register
should be read.
SCSI-type and DMA-type interrupts may occur simultaneously, so in
some cases both SIP and DIP may be set.
SIST0 and SIST1 – The
SCSI Interrupt Status Zero (SIST0)
and
SCSI Interrupt Status One (SIST1)
registers contain SCSI-type interrupt
bits. Reading these registers determines which condition or conditions
caused the SCSI-type interrupt, and clears that SCSI interrupt condition.
If the LSI53C896 is receiving data from the SCSI bus and a fatal interrupt
condition occurs, the chip attempts to send the contents of the DMA
FIFO to memory before generating the interrupt.
If the LSI53C896 is sending data to the SCSI bus and a fatal SCSI interrupt
condition occurs, data could be left in the DMA FIFO. Because of this the
DMA FIFO Empty (DFE) bit in
should be checked.
•
If this bit is cleared, set the Clear DMA FIFO (CLF) and Clear SCSI
FIFO (CSF) bits before continuing. The CLF bit is bit 2 in
. The CSF bit is bit 1 in
.
DSTAT – The
register contains the DMA-type
interrupt bits. Reading this register determines which condition or
conditions caused the DMA-type interrupt, and clears that DMA interrupt
condition. Bit 7 in DSTAT, DFE, is purely a status bit; it does not generate
an interrupt under any circumstances and is not cleared when read. DMA