Avago Technologies LSI53C896 - Manual (Page 337)

Package Drawings 6-69
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Table 6.51 Alphanumeric List by BGA Position
NC A1
NC A2
A_SD12+ A3
A_SD13+ A4
A_SD15+ A5
A_SD0+ A6
A_SD2
−
A7
A_SD4 − A8
A_SD6
−
A9
A_SDP0
−
A10
VDD-BIAS2 A11
A_SBSY+ A12
A_SACK2+ A13
A_SACK+ A14
A_SMSG+ A15
A_SC_D+ A16
A_SREQ+ A17
A_SD8
−
A18
A_SD10
−
A19
A_DIFFSENS A20
SCLK A21
NC A22
NC A23
AD1 AA1
REQ64/ AA2
VSS AA3
C_BE7/ AA4
PAR64 AA5
AD60 AA6
AD56 AA7
AD53 AA8
AD49 AA9
AD45 AA10
AD41 AA11
AD37 AA12
AD33 AA13
B_GPIO0_
FETCH/ AA14
B_GPIO3 AA15
A_GPIO2 AA16
MAS1/ AA17
MCE/ AA18
MAD[6] AA19
MAD[3] AA20
VSS AA21
NC AA22
B_SD11+ AA23
ACK64/ AB1
NC AB2
NC AB3
C_BE5/ AB4
AD62 AB5
AD58 AB6
AD55 AB7
AD51 AB8
AD47 AB9
AD43 AB10
AD39 AB11
AD36 AB12
AD35 AB13
RESERVED AB14
B_GPIO2 AB15
A-GPIO0_
FETCH/ AB16
A_GPIO4 AB17
VDD-CORE AB18
VSS-CORE AB19
MAD[4] AB20
MAD[1] AB21
NC AB22
NC AB23
NC AC1
NC AC2
C_BE6/ AC3
C_BE4/ AC4
AD61 AC5
AD57 AC6
AD54 AC7
AD50 AC8
AD46 AC9
AD42 AC10
AD40 AC11
AD38 AC12
AD34 AC13
AD32 AC14
B_GPIO1_
MASTER/ AC15
B_GPIO4 AC16
A_GPIO3 AC17
MAS0/ AC18
MWE/ AC19
MAD[5] AC20
VSS-CORE AC21
MAD[2] AC22
MAD[0] AC23
NC B1
NC B2
NC B3
A_SD13
−
B4
A_SD15
−
B5
A_SD0
−
B6
A_SD1+ B7
A_SD3+ B8
A_SD5+ B9
A_SD7+ B10
A_SATN
−
B11
A_SATN+ B12
A_SACK2
−
B13
A_SRST
−
B14
A_SSEL
−
B15
A_SREQ2
−
B16
A_SI_O
−
B17
A_SD8+ B18
A_SD10+ B19
VSS-A B20
NC B21
NC B22
NC B23
TEST_RST/ C1
NC C2
VSS C3
A_SD12
−
C4
A_SD14
−
C5
A_SDP1
−
C6
A_SD1
−
C7
A_SD2+ C8
A_SD4+ C9
A_SD6+ C10
A_SDP0+ C11
A_SBSY
−
C12
A_SACK
−
C13
A_SMSG
−
C14
A_SC_D
−
C15
A_SREQ
−
C16
A_SI_O+ C17
A_SD9+ C18
A_SD11+ C19
VDD-A C20
VSS C21
NC C22
TEST_HSC C23
TCK D1
VSS-CORE D2
VDD-CORE D3
VSS D4
A_SD14+ D5
A_SDP1+ D6
VDD D7
A_SD3
−
D8
A_SD5
−
D9
VDD D10
A_SD7
−
D11
VSS D12
A_SRST+ D13
VDD D14
A_SSEL+ D15
A_SREQ2+ D16
VDD D17
A_SD9
−
D18
A_SD11
−
D19
VSS D20
NC D21
B_SD12
−
D22
B_SD12+ D23
TDO E1
TDI E2
TMS E3
VDD-CORE E4
B_SD13+ E20
B_SD13
−
E21
B_SD14
−
E22
B_SD14+ E23
ALT_INTA/ F1
INTB/ F2
VSS_CORE F3
INTA/ F4
B_SD15+ F20
B_SD15
−
F21
B_SDP1
−
F22
B_SDP1+ F23
RST/ G1
INT_DIR G2
ALT_INTB/ G3
VDD G4
VDD G20
B_SD0
−
G21
B_SD0+ G22
B_SD1
−
G23
AD31 H1
REQ/ H2
CLK H3
GNT/ H4
B_SD2
−
H20
B_SD1+ H21
B_SD2+ H22
B_SD3- H23
AD27 J1
AD28 J2
AD30 J3
AD29 J4
B_SD4
−
J20
B_SD3+ J21
B_SD4+ J22
B_SD5
−
J23
C_BE3/ K1
AD24 K2
AD26 K3
VDD K4
VSS K10
VSS K11
VSS K12
VSS K13
VSS K14
VDD K20
B_SD5+ K21
B_SD6+ K22
B_SD7
−
K23
AD23 L1
AD22 L2
IDSEL L3
AD25 L4
VSS L10
VSS L11
VSS L12
VSS L13
VSS L14
B_SD6
−
L20
B_SD7+ L21
B_SDP0+ L22
B_SDP0
−
L23
AD21 M1
AD19 M2
AD20 M3
VSS M4
VSS M10
VSS M11
VSS M12
VSS M13
VSS M14
VSS M20
RBIAS M21
VDD-BIAS M22
B_SATN
−
M23
AD17 N1
AD18 N2
AD16 N3
IRDY/ N4
VSS N10
VSS N11
VSS N12
VSS N13
VSS N14
B_SACK
−
N20
B_SBSY+ N21
B_SATN+ N22
B_SBSY
−
N23
C_BE2/ P1
FRAME/ P2
TRDY/ P3
VDD P4
VSS P10
VSS P11
VSS P12
VSS P13
VSS P14
VDD P20
B_SACK+ P21
B_SACK2+ P22
B_SACK2 − P23
DEVSEL/ R1
STOP/ R2
SERR/ R3
PERR/ R4
B_SMSG
−
R20
B_SMSG+ R21
B_SRST+ R22
B_SRST − R23
PAR T1
C_BE1/ T2
AD14 T3
AD15 T4
B_SC_D
−
T20
B_SC_D+ T21
B_SSEL+ T22
B_SSEL − T23
AD13 U1
AD12 U2
AD11 U3
VDD U4
VDD U20
B_SREQ
−
U21
B_SREQ2+ U22
B_SREQ2 − U23
AD10 V1
AD9 V2
C_BE0/ V3
AD8 V4
B_SI_O+ V20
B_SD8
−
V21
B_SI_O
−
V22
B_SREQ+ V23
AD7 W1
AD6 W2
AD4 W3
AD5 W4
B_SD9+ W20
B_SD10
−
W21
B_SD9
−
W22
B_SD8+ W23
AD3 Y1
AD2 Y2
AD0 Y3
VSS Y4
AD63 Y5
AD59 Y6
VDD Y7
AD52 Y8
AD48 Y9
VDD Y10
AD44 Y11
VSS Y12
VDD-CORE Y13
VDD Y14
VSS-CORE Y15
A_GPIO1_
MASTER/ Y16
VDD Y17
MOE/_TESTOUT Y18
MAD[7] Y19
VSS Y20
B_DIFFSENS Y21
B_SD11
−
Y22
B_SD10+ Y23
Signal BGA
Name Pos
Signal BGA
Name Pos
Signal BGA
Name Pos
Signal BGA
Name Pos
Signal BGA
Name Pos