Avago Technologies LSI53C896 - Manual (Page 17)

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6.29 Burst Write, 32-Bit Address and Data 6-34
6.30 Burst Write, 64-Bit Address and Data 6-36
6.31 External Memory Read 6-39
6.32 External Memory Write 6-43
6.33 Normal/Fast Memory (
≥
128 Kbytes) Single Byte
Access Read Cycle 6-46
6.34 Normal/Fast Memory (
≥
128 Kbytes) Single Byte
Access Write Cycle 6-48
6.35 Slow Memory (
≥
128 Kbytes) Read Cycle 6-54
6.36 Slow Memory (
≥
128 Kbytes) Write Cycle 6-56
6.37
≤
64 Kbytes ROM Read Cycle 6-58
6.38
≤
64 Kbytes ROM Write Cycle 6-59
6.39 Initiator Asynchronous Send 6-60
6.40 Initiator Asynchronous Receive 6-61
6.41 Target Asynchronous Send 6-61
6.42 Target Asynchronous Receive 6-62
6.43 SCSI-1 Transfers (SE 5.0 Mbytes) 6-63
6.44 SCSI-1 Transfers (Differential 4.17 Mbytes) 6-63
6.45 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or
20.0 Mbytes (16-Bit Transfers) 40 MHz Clock
6-64
6.46 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or
20.0 Mbytes (16-Bit Transfers) 50 MHz Clock
6-64
6.47 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or
40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock
6-65
6.48 Ultra SCSI HVD Transfers 20.0 Mbytes (8-Bit Transfers)
or 40.0 Mbytes (16-Bit Transfers) 80 MHz Clock
6-65
6.49 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or
80.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock
6-66
6.50 Alphanumeric List by Signal Name 6-68
6.51 Alphanumeric List by BGA Position 6-69
A.1 LSI53C896 Register Map A-1