Chip test three (ctest3), Register: 0x1b – Avago Technologies LSI53C896 User Manual
Page 170
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Registers
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
TEOP
SCSI True End of Process
2
This bit indicates the status of the LSI53C896 SCSI
function’s internal TEOP signal. The TEOP signal
acknowledges the completion of a transfer through the
SCSI portion of the LSI53C896 SCSI function. When this
bit is set, TEOP is active. When this bit is cleared, TEOP
is inactive.
DREQ
Data Request Status
1
This bit indicates the status of the LSI53C896 SCSI
function’s internal Data Request signal (DREQ). When
this bit is set, DREQ is active. When this bit is cleared,
DREQ is inactive.
DACK
Data Acknowledge Status
0
This bit indicates the status of the LSI53C896 SCSI
function’s internal Data Acknowledge signal (DACK/).
When this bit is set, DACK/ is inactive. When this bit is
cleared, DACK/ is active.
Register: 0x1B
Chip Test Three (CTEST3)
Read/Write
V
Chip Revision Level
[7:4]
These bits identify the chip revision level for software
purposes. It should have the same value as the lower
nibble of the PCI
register. These bits
are read only.
FLF
Flush DMA FIFO
3
When this bit is set, data residing in the DMA FIFO is
transferred to memory, starting at the address in the
register. The internal DMAWR
signal, controlled by the
register,
determines the direction of the transfer. This bit is not
self-clearing; clear it when the data is successfully
transferred by the LSI53C896 SCSI function.
Note:
Polling of FIFO flags is allowed during flush operations.
7
4
3
2
1
0
V
FLF
CLF
FM
WRIE
x
x
x
x
0
0
0
1