7 opcode fetch burst capability, 8 load/store instructions, Opcode fetch burst capability – Avago Technologies LSI53C896 User Manual
Page 53: Load/store instructions
SCSI Functional Description
2-25
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
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On every Store instruction.
The Store instruction also may place modified code directly into
memory. To avoid inadvertently flushing the prefetch unit contents,
use the No Flush option for all Store operations that do not modify
code within the next 8 Dwords.
•
On every write to the
register.
•
On all Transfer Control instructions when the transfer conditions
are met.
This is necessary because the next instruction to execute is not the
sequential next instruction in the prefetch unit.
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When the Prefetch Flush bit (
register, bit 6)
is set. The unit flushes whenever this bit is set. The bit is
self-clearing.
2.2.7 Opcode Fetch Burst Capability
Setting the Burst Opcode Fetch Enable bit (bit 1) in the
register (0x38) causes the LSI53C896 to burst in
the first two Dwords of all instruction fetches. If the instruction is a
Memory-to-Memory Move, the third Dword is accessed in a separate
ownership. If the instruction is an Indirect Type, the additional Dword is
accessed in a subsequent bus ownership. If the instruction is a table
indirect Block Move, the chip uses two accesses to obtain the four
Dwords required, in two bursts of two Dwords each.
Note:
This feature is only useful if Prefetching is disabled.
This feature is only useful if fetching SCRIPTS instructions
from main memory. Due to the short access time of
SCRIPTS RAM, burst opcode fetching is not necessary
when fetching instructions from this memory.
2.2.8 Load/Store Instructions
The LSI53C896 supports the Load/Store instruction type, which simplifies
the movement of data between memory and the internal chip registers. It
also enables the chip to transfer bytes to addresses relative to the
register. Load/Store data transfers to or
from the SCRIPTS RAM remain internal to the chip and do not generate
PCI bus cycles. While a Load/Store to or from SCRIPTS RAM is