Scsi interrupt status zero (sist0), Register: 0x42 – Avago Technologies LSI53C896 User Manual

Page 191

SCSI Registers

4-79

Version 3.3

HTH

Handshake-to-Handshake Timer Expired

The handshake-to-handshake timer is expired. The time
measured is the SCSI Request-to-Request (target) or
Acknowledge-to-Acknowledge (initiator) period. Refer to
the description of the

SCSI Timer Zero (STIME0)

bits [7:4], for details on the handshake-to-handshake timer.

Register: 0x42

SCSI Interrupt Status Zero (SIST0)
Read Only

Reading the

SCSI Interrupt Status Zero (SIST0)

status of the various interrupt conditions, whether they are enabled in the

SCSI Interrupt Enable Zero (SIEN0)

occurrence of the corresponding condition. Reading the SIST0 clears the
interrupt status.

Reading this register clears any bits that are set at the time the register
is read, but does not necessarily clear the register because additional
interrupts may be pending (the LSI53C896 SCSI functions stack
interrupts). SCSI interrupt conditions are individually masked through the

SCSI Interrupt Enable Zero (SIEN0)

When performing consecutive 8-bit reads of the

DMA Status (DSTAT)

SCSI Interrupt Status Zero (SIST0)

, and

SCSI Interrupt Status One (SIST1)

registers (in any order), insert a delay equivalent to 12 clock periods
between the reads to ensure the interrupts clear properly. Also, if reading
the registers when both the

Interrupt Status Zero (ISTAT0)

SIP and DIP bits

may not be set, read the SIST0 and SIST1 registers before the DSTAT
register to avoid missing a SCSI interrupt. For details on interrupts refer to

Chapter 2, “Functional Description.”

M/A

Initiator Mode: Phase Mismatch; Target Mode:
SATN/ Active

In the initiator mode, this bit is set if the SCSI phase
asserted by the target does not match the instruction.
The phase is sampled when SREQ/ is asserted by the
target. In the target mode, this bit is set when the SATN/
signal is asserted by the initiator.

M/A

CMP

SEL

RSL

SGE

UDC

RST

PAR