17 interrupt handling, Interrupt handling – Avago Technologies LSI53C896 User Manual
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SCSI Functional Description
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2.2.17 Interrupt Handling
The SCRIPTS processors in the LSI53C896 perform most functions
independently of the host microprocessor. However, certain interrupt
situations must be handled by the external microprocessor. This section
explains all aspects of interrupts as they apply to the LSI53C896.
2.2.17.1 Polling and Hardware Interrupts
The external microprocessor is informed of an interrupt condition by
polling or hardware interrupts. Polling means that the microprocessor
must continually loop and read a register until it detects a bit that is set
indicating an interrupt. This method is the fastest, but it wastes CPU time
that could be used for other system tasks. The preferred method of
detecting interrupts in most systems is hardware interrupts. In this case,
the LSI53C896 asserts the Interrupt Request (INTA/ or INTB/) line that
interrupts the microprocessor, causing the microprocessor to execute an
interrupt service routine. A hybrid approach would use hardware
interrupts for long waits, and use polling for short waits.
SCSI Function A is routed to PCI Interrupt INTA/. SCSI Function B is
normally routed to INTB/, but can be routed to INTA/ if a pull-up is
connected to MAD[4]. Refer to
Section 3.7, “MAD Bus Programming,”
for details.
2.2.17.2 Registers
The registers in the LSI53C896 that are used for detecting or defining
interrupts are ISTAT;
SCSI Interrupt Status Zero (SIST0)
;
SCSI Interrupt Status One (SIST1)
SCSI Interrupt Enable Zero (SIEN0)
;
SCSI Interrupt Enable One (SIEN1)
; and
.
ISTAT – The ISTAT register includes the
Interrupt Status Zero (ISTAT0)
, and
registers. It is the only register that can be accessed
as a slave during the SCRIPTS operation. Therefore, it is the register that
is polled when polled interrupts are used. It is also the first register that
should be read after the INTA/ (or INTB/) pin is asserted in association with
a hardware interrupt. The Interrupt-on-the-Fly (INTF) bit should be the first
interrupt serviced. It must be written to one to be cleared. This interrupt
must be cleared before servicing any other interrupts.