Avago Technologies LSI53C896 - Manual (Page 15)

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Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Tables
2.1 PCI Bus Commands and Encoding Types 2-5
2.2 PCI Cache Mode Alignment 2-14
2.3 Bits Used for Parity Control and Generation 2-28
2.4 SCSI Parity Control 2-29
2.5 SCSI Parity Errors and Interrupts 2-29
2.6 HVD Signals 2-36
2.7 Parallel ROM Support 2-56
2.8 Mode A Serial EEPROM Data Format 2-58
2.9 Power States 2-59
3.1 LSI53C896 Internal Pull-ups and Pull-downs 3-4
3.2 System Signals 3-5
3.3 Address and Data Signals 3-6
3.4 Interface Control Signals 3-7
3.5 Arbitration Signals 3-8
3.6 Error Reporting Signals 3-9
3.7 Interrupt Signals 3-10
3.8 SCSI Function A GPIO Signals 3-11
3.9 SCSI Function B GPIO Signals 3-12
3.10 SCSI Bus Interface Signals 3-13
3.11 SCSI Function A Signals 3-14
3.12 SCSI Function A_SCTRL Signals 3-15
3.13 SCSI Function B Signals 3-16
3.14 SCSI Function B_SCRTL Signals 3-18
3.15 Flash ROM and Memory Interface Signals 3-19
3.16 Test Interface Signals 3-20
3.17 Power and Ground Signals 3-21
3.18 Decode of MAD[3:1] Pins 3-23
4.1 PCI Configuration Register Map 4-2
4.2 SCSI Register Map 4-20
4.3 Examples of Synchronous Transfer Periods and Rates
for SCSI-1
4-34
4.4 Example Transfer Periods and Rates for Fast SCSI-2,
Ultra, and Ultra2
4-35
4.5 Maximum Synchronous Offset 4-36
4.6 SCSI Synchronous Data FIFO Word Count 4-46
5.1 Read/Write Instructions 5-25