Avago Technologies LSI53C896 - Manual (Page 263)

Memory Move Instructions 5-35
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
5.6.1 First Dword
Figure 5.12 Memory Move Instructions – First Dword
IT[2:0] Instruction Type – Memory Move [31:29]
R Reserved [28:25]
These bits are reserved and must be zero. If any of these
bits are set, an illegal instruction interrupt occurs.
NF No Flush 24
When this bit is set, the LSI53C896 performs a
Memory Move without flushing the prefetch unit. When
this bit is cleared, the Memory Move instruction automat-
ically flushes the prefetch unit. Use the No Flush option
if the source and destination are not within four
instructions of the current Memory Move instruction.
Note: This bit has no effect unless the Prefetch Enable bit in the
DMA Control (DCNTL) register is set. For details on
SCRIPTS instruction prefetching, refer to
Chapter 2, "Functional Description."
TC[23:0] Transfer Count [23:0]
The number of bytes to transfer is stored in the lower
24 bits of the first instruction word.
5.6.2 Read/Write System Memory from a SCRIPTS
By using the Memory Move instruction, single or multiple register values
are transferred to or from system memory.
Because the LSI53C896 responds to addresses as defined in the
Base Address Register Zero (I/O) or
Base Address Register One (MEMORY) registers, it can be accessed
during a Memory Move operation if the source or destination address
decodes to within the chip’s register space. If this occurs, the register
indicated by the lower seven bits of the address is taken as the data
31 29 28 25 24 23 0
DCMD Register DBC Register
IT[2:0] R NF TC[23:0]