Avago Technologies LSI53C896 - Manual (Page 219)

64-Bit SCRIPTS Selectors 4-107
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
4.3 64-Bit SCRIPTS Selectors
The following registers hold the upper 32-bit addresses for various
SCRIPTS operations. When a particular type of SCRIPTS operation is
performed, one of the following six selector registers generates a 64-bit
address.
If the selector for a particular device operation is zero, then a standard
32-bit address cycle is generated. If the selector value is nonzero, then
a DAC is issued with the entire 64-bit address.
All selectors default to 0 (zero) with the exception of the 16 scratch
registers, these power-up in an indeterminate state and should be
initialized before they are used.
All selectors can be read/written using the Load/Store SCRIPTS
instruction, Memory-to-Memory Move, Read/Write SCRIPTS instruction
or CPU with SCRIPTS not running.
Note: Crossing of selector boundaries in one memory operation
is not supported.
Registers: 0xA0–0xA3
Memory Move Read Selector (MMRS)
Read/Write
MMRS Memory Move Read Selector (MMRS) [31:0]
Supplies AD[63:32] during data read operations for
Memory-to-Memory Moves and absolute address
LOAD operations.
A special mode of this register can be enabled by setting
the PCI Configuration Info Enable bit in the
Chip Test Two (CTEST2) register. If this bit is set, the
Memory Move Read Selector (MMRS) register returns
bits [63:32] of the memory mapped operating register,
PCI
Base Address Register One (MEMORY) , when read.
31 0
MMRS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0