Avago Technologies LSI53C896 - Manual (Page 190)

4-78 Registers
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x41
SCSI Interrupt Enable One (SIEN1)
Read/Write
This register contains the interrupt mask bits corresponding to the
interrupting conditions described in the
SCSI Interrupt Status One (SIST1)
register. An interrupt is masked by clearing the appropriate mask bit. For
details on interrupts refer to
Chapter 2, “Functional Description.”
R Reserved [7:5]
SBMC SCSI Bus Mode Change 4
Setting this bit allows the LSI53C896 to generate an
interrupt when the DIFFSENS pin detects a change in
voltage level that indicates the SCSI bus has changed
between SE, LVD, or HVD modes. For example, when this
bit is cleared and the SCSI bus changes modes, IRQ/
does not assert and the SIP bit in the
Interrupt Status Zero (ISTAT0) register is not set.
However, bit 4 in the SCSI Interrupt Status One (SIST1)
register is set. Setting this bit allows the interrupt to occur.
R Reserved 3
STO Selection or Reselection Time-out 2
The SCSI device which the LSI53C896 SCSI function is
attempting to select or reselect does not respond within
the programmed time-out period. Refer to the description
of the
SCSI Timer Zero (STIME0) register bits [3:0] for
details on the time-out timer.
GEN General Purpose Timer Expired 1
The general purpose timer is expired. The time measured
is the time between enabling and disabling of the timer.
Refer to the description of the
SCSI Timer One (STIME1)
register, bits [3:0], for details on the general purpose timer.
7 5 4 3 2 1 0
R SBMC R STO GEN HTH
x x x x x 0 0 0