Avago Technologies LSI53C896 - Manual (Page 215)

SCSI Registers 4-103
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
R Reserved [3:2]
DILS Disable Internal Load/Store 1
This bit controls whether or not Load/Store data transfers,
in which the source/destination is located in SCRIPTS
RAM, generate external PCI cycles.
If cleared, Load/Store data transfers of this type do not
generate PCI cycles, but stay internal to the chip.
If set, Load/Store data transfers of this type generate
PCI cycles.
DPR Disable Pipe Req 0
This bit controls whether or not overlapped arbitration on
the PCI bit is performed by asserting PCI REQ/ for one
SCSI function while the other SCSI function is executing
a PCI cycle.
If set, overlapped arbitration is disabled, and PCI REQ/ is
not asserted during a PCI master cycle being executed
by this chip.
Register: 0x57
Chip Control 1 (CCNTL1)
Read/Write
ZMOD High Impedance Mode 7
Setting this bit causes the LSI53C896 SCSI function to
place all output and bidirectional pins except
MOE/_TESTOUT, into a high impedance state. When this
bit is set, the MOE/_TESTOUT pin becomes the output
pin for the connectivity test of the LSI53C896 signals in
the “AND-tree” test mode. In order to read data out of the
LSI53C896 SCSI function, this bit must be cleared. This
bit is intended for board-level testing only. Do not set this
bit during normal system operation.
Note: Both SCSI functions need to set this bit for the high
impedance mode.
7 6 4 3 2 1 0
ZMOD R DDAC 64TIMOD EN64TIBMV EN64DBMV
0 0 0 0 x x 0 0