Avago Technologies LSI53C896 - Manual (Page 155)

SCSI Registers 4-43
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
R Reserved 1
IID Illegal Instruction Detected 0
This status bit is set any time an illegal or reserved
instruction opcode is detected, whether the LSI53C896
SCSI function is operating in single step mode or
automatically executing SCSI SCRIPTS.
Any of the following conditions during instruction
execution also sets this bit:
•
The LSI53C896 SCSI function is executing a
Wait Disconnect instruction and the SCSI REQ line is
asserted without a disconnect occurring.
•
A Block Move instruction is executed with 0x000000
loaded into the
DMA Byte Counter (DBC) register,
indicating there are zero bytes to move.
•
During a Transfer Control instruction, the
Compare Data (bit 18) and Compare Phase (bit 17)
bits are set in the
DMA Byte Counter (DBC) register
while the LSI53C896 SCSI function is in target mode.
•
During a Transfer Control instruction, the Carry Test
bit (bit 21) is set and either the Compare Data (bit 18)
or Compare Phase (bit 17) bit is set.
•
A Transfer Control instruction is executed with the
reserved bit 22 set.
•
A Transfer Control instruction is executed with the
Wait for Valid phase bit (bit 16) set while the chip is in
target mode.
•
A Load/Store instruction is issued with the memory
address mapped to the operating registers of the chip,
not including ROM or RAM.
•
A Load/Store instruction is issued when the register
address is not aligned with the memory address.
•
A Load/Store instruction is issued with bit 5 in the
DMA Command (DCMD) register cleared or bits 3 or
2 set.
•
A Load/Store instruction when the count value in the
DMA Byte Counter (DBC) register is not set at 1 to 4.
•
A Load/Store instruction attempts to cross a Dword
boundary.