Avago Technologies LSI53C896 - Manual (Page 8)

viii Contents
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
2.2.9 JTAG Boundary Scan Testing 2-26
2.2.10 SCSI Loopback Mode 2-26
2.2.11 Parity Options 2-27
2.2.12 DMA FIFO 2-31
2.2.13 Data Paths 2-32
2.2.14 SCSI Bus Interface 2-35
2.2.15 Select/Reselect during Selection/Reselection 2-40
2.2.16 Synchronous Operation 2-40
2.2.17 Interrupt Handling 2-43
2.2.18 Interrupt Routing 2-50
2.2.19 Chained Block Moves 2-52
2.3 Parallel ROM Interface 2-55
2.4 Serial EEPROM Interface 2-57
2.4.1 Default Download Mode 2-57
2.4.2 No Download Mode 2-58
2.5 Power Management 2-58
2.5.1 Power State D0 2-59
2.5.2 Power State D1 2-59
2.5.3 Power State D2 2-60
2.5.4 Power State D3 2-60
Chapter 3 Signal Descriptions
3.1 Internal Pull-ups on LSI53C896 Signals 3-4
3.2 PCI Bus Interface Signals 3-5
3.2.1 System Signals 3-5
3.2.2 Address and Data Signals 3-6
3.2.3 Interface Control Signals 3-7
3.2.4 Arbitration Signals 3-8
3.2.5 Error Reporting Signals 3-9
3.2.6 Interrupt Signals 3-10
3.2.7 SCSI Function A GPIO Signals 3-11
3.2.8 SCSI Function B GPIO Signals 3-12
3.3 SCSI Bus Interface Signals 3-13
3.3.1 SCSI Function A Signals 3-13
3.3.2 SCSI Function B Signals 3-16
3.4 Flash ROM and Memory Interface Signals 3-19
3.5 Test Interface Signals 3-20