Avago Technologies LSI53C896 - Manual (Page 341)

LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller A-1
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Appendix A
Register Summary
Table A.1 lists the PCI and SCSI registers by register name for
the LSI53C896.
Table A.1 LSI53C896 Register Map
Register Name Address Read/Write Page
PCI Registers
Base Address Register One (MEMORY) 0x14–0x1B Read/Write 4-9
Base Address Register Two (SCRIPTS RAM) 0x1C–0x23 Read/Write 4-10
Base Address Register Zero (I/O) 0x10–0x13 Read/Write 4-9
Bridge Support Extensions (PMCSR_BSE) 0x46 Read Only 4-19
Cache Line Size 0x0C Read/Write 4-7
Capabilities Pointer 0x34 Read Only 4-14
Capability ID 0x40 Read Only 4-16
Class Code 0x09–0x0B Read Only 4-7
Command 0x04–0x05 Read/Write 4-3
Data 0x47 Read Only 4-19
Device ID 0x02–0x03 Read Only 4-3
Expansion ROM Base Address 0x30–0x33 Read/Write 4-13
Header Type 0x0E Read Only 4-8
Interrupt Line 0x3C Read/Write 4-14
Interrupt Pin 0x3D Read Only 4-15
Latency Timer 0x0D Read/Write 4-8