Avago Technologies LSI53C896 User Manual
Page 355

Index
IX-5
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
B_SI_O+-
B_SMSG+-
B_SREQ+-
B_SREQ2+-
B_SRST+-
B_SSEL+-
back-to-back read
32-bits address and data
back-to-back write
32-bits address and data
base address register
one (BARO)
,
two (BART)
zero (BARZ)
bidirectional
signals
BIOS
bits used for parity control and generation
block move
instructions
bridge support extensions (BSE)
burst
disable (BDIS)
length (BL)
length bit 2 (BL2)
opcode fetch
32-bits address and data
opcode fetch enable (BOF)
size selection
burst read
32-bits address and data
64-bits address and data
burst write
32-bits address and data
bus
command and byte enables
fault (BF)
,
byte
count
empty in DMA FIFO (FMT)
full in DMA FIFO (FFL)
offset counter (BO)
C
C_BE[3:0]/
C_BE[7:0]/
cache line size
(CLS)
,
enable (CLSE)
,
register
cache mode, see PCI cache mode
call instruction
Cap_ID (CID)
capabilities pointer (CP)
capability ID register
carry test
chained block moves
SCRIPTS instruction
SODL register
SWIDE register
wide SCSI receive bit
wide SCSI send bit
chained mode (CHM)
change bus phases
chip
control 0 (CCNTL0)
control 1 (CCNTL1)
revision level (V)
test five (CTEST5)
test four (CTEST4)
,
test one (CTEST1)
test six (CTEST6)
test three (CTEST3)
,
,
test two (CTEST2)
test zero (CTEST0)
type (CTYPE)
type (TYP)
CHMOV
class code register
clear DMA FIFO (CLF)
,
clear instruction
clear SCSI FIFO (CSF)
,
CLK
clock
address incrementor (ADCK)
byte counter (BBCK)
conversion factor (CCF[2:0])
quadrupler
compare
data
phase
configuration
read command
space
write command
configured
as I/O (CIO)
as memory (CM)
connected (CON)
,
cumulative SCSI byte count (CSBC)
current
function of input voltage
function of output voltage
cycle frame