Avago Technologies LSI53C896 - Manual (Page 85)

Serial EEPROM Interface 2-57
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
The LSI53C896 allows the system to determine the size of the available
external memory using the
Expansion ROM Base Address register in the
PCI configuration space. For details on how this works, refer to the PCI
specification or the Expansion ROM Base Address register description in
Chapter 4, “Registers.”
MAD[0] is the slow ROM pin. When pulled up, it enables two extra clock
cycles of data access time to allow use of slower memory devices. The
external memory interface also supports updates to flash memory.
2.4 Serial EEPROM Interface
The LSI53C896 implements an interface that allows attachment of a
serial EEPROM device to the GPIO0 and GPIO1 pins for each SCSI
function. There are two modes of operation relating to the serial
EEPROM and the
Subsystem ID and Subsystem Vendor ID registers for
each SCSI function. These modes are programmable through the
MAD[7] pin which is sampled at power-up or hard reset.
2.4.1 Default Download Mode
In this mode, MAD[7] is pulled down internally, GPIO0 is the serial data
signal (SDA) and GPIO1 is the serial clock signal (SCL). Certain data in
the serial EEPROM is automatically loaded into chip registers at
power-up or hard reset.
The format of the serial EEPROM data is defined in Table 2.8 . If the
download is enabled and an EEPROM is not present, or the checksum
fails, the
Subsystem ID and Subsystem Vendor ID registers read back all
zeros. At power-up or hard reset, only five bytes are loaded into the chip
from locations 0xFB through 0xFF.
The Subsystem ID and Subsystem Vendor ID registers are read only, in
accordance with the PCI specification, with a default value of all zeros if
the download fails.