Avago Technologies LSI53C896 User Manual
Page 174
4-62
Registers
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Move operation. The
and
registers contain the base address
used for table indirect calculations, and the address
pointer for a call or return instruction, respectively. This
bit is intended for manufacturing diagnostics only and
should not be set during normal operations.
MPEE
Master Parity Error Enable
3
Setting this bit enables parity checking during master
data phases. A parity error during a bus master read is
detected by the LSI53C896 SCSI function. A parity error
during a bus master write is detected by the target, and
the LSI53C896 SCSI function is informed of the error by
the PERR/ pin being asserted by the target. When this bit
is cleared, the LSI53C896 SCSI function does not
interrupt if a master parity error occurs. This bit is cleared
at power-up.
FBL[2:0]
FIFO Byte Control
[2:0]
These bits steer the contents of the
register to the appropriate byte
lane of the 64-bit DMA FIFO. If the FBL3 bit is set, then
FBL2 through FBL0 determine which of eight byte lanes
can be read or written. When cleared, the byte lane read
or written is determined by the current contents of the
and
registers. Each of the eight bytes that make up the 64-bit
DMA FIFO is accessed by writing these bits to the proper
value. For normal operation, FBL3 must equal zero.
FBL3
FBL2
FBL1
FBL0
DMA FIFO
Byte Lane
Pins
0
x
x
x
Disabled
n/a
1
0
0
0
0
D[7:0]
1
0
0
1
1
D[15:8]
1
0
1
0
2
D[23:16]
1
0
1
1
3
D[31:24]
1
1
0
0
4
D[39:32]
1
1
0
1
5
D[47:40]
1
1
1
0
6
D[53:48]
1
1
1
1
7
D[63:54]