Avago Technologies LSI53C896 - Manual (Page 74)

2-46 Functional Description
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
When operating in the Target mode, CMP, SEL, RSL, Target mode:
SATN/ active (M/A), GEN, and HTH are nonfatal. Refer to the description
for the Disable Halt on a Parity Error or SATN/ active (Target Mode Only)
(DHP) bit in the
SCSI Control One (SCNTL1) register to configure the
chip’s behavior when the SATN/ interrupt is enabled during Target mode
operation. The Interrupt-on-the-Fly interrupt is also nonfatal, because
SCRIPTS can continue when it occurs.
The reason for nonfatal interrupts is to prevent the SCRIPTS from
stopping when an interrupt occurs that does not require service from the
CPU. This prevents an interrupt when arbitration is complete (CMP set),
when the LSI53C896 is selected or reselected (SEL or RSL set), when
the initiator asserts ATN (target mode: SATN/ active), or when the
General Purpose or Handshake-to-Handshake timers expire. These
interrupts are not needed for events that occur during high-level
SCRIPTS operation.
2.2.17.4 Masking
Masking an interrupt means disabling or ignoring that interrupt. Interrupts
can be masked by clearing bits in the
SCSI Interrupt Enable Zero (SIEN0)
and SCSI Interrupt Enable One (SIEN1) (for SCSI interrupts) registers or
DMA Interrupt Enable (DIEN) (for DMA interrupts) register. How the chip
responds to masked interrupts depends on: whether polling or hardware
interrupts are being used; whether the interrupt is fatal or nonfatal; and
whether the chip is operating in the Initiator or Target mode.
If a nonfatal interrupt is masked and that condition occurs, the SCRIPTS
do not stop, the appropriate bit in the
SCSI Interrupt Status Zero (SIST0)
or SCSI Interrupt Status One (SIST1) is still set, the SIP bit in the
Interrupt Status Zero (ISTAT0) is not set, and the INTA/ (or INTB/) pin is
not asserted.
If a fatal interrupt is masked and that condition occurs, then the SCRIPTS
still stop, the appropriate bit in the
DMA Status (DSTAT) ,
SCSI Interrupt Status Zero (SIST0) , or SCSI Interrupt Status One (SIST1)
register is set, and the SIP or DIP bit in the Interrupt Status Zero (ISTAT0)
register is set, but the INTA/ (or INTB/) pin is not asserted.
Interrupts can be disabled by setting the SYNC_IRQD bit in the
Interrupt Status One (ISTAT1) register. If an interrupt is already asserted
and SYNC_IRQD is then set, the interrupt remains until serviced. Further
interrupts are blocked.