Avago Technologies LSI53C896 - Manual (Page 240)

5-12 SCSI SCRIPTS Instruction Set
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Initiator Mode
The LSI53C896 verifies that it is connected to the SCSI
bus as an initiator before executing this instruction.
The LSI53C896 waits for an unserviced phase to occur.
An unserviced phase is defined as any phase
(with SREQ/ asserted) for which the LSI53C896 has not
yet transferred data by responding with a SACK/.
The LSI53C896 compares the SCSI phase bits in the
DMA Command (DCMD) register with the latched SCSI
phase lines stored in the SCSI Status One (SSTAT1)
register. These phase lines are latched when SREQ/
is asserted.
If the SCSI phase bits match the value stored in the
SCSI Status One (SSTAT1) register, the LSI53C896
transfers the number of bytes specified in the
DMA Byte Counter (DBC) register starting at the address
pointed to by the DMA Next Address (DNAD) register. If
the opcode bit is cleared and a data transfer ends on an
odd byte boundary, the LSI53C896 stores the last byte in
the
SCSI Wide Residue (SWIDE) register during a
receive operation, or in the SCSI Output Data Latch
(SODL) register during a send operation. This byte is
combined with the first byte from the subsequent transfer
so that a wide transfer can complete.
If the SCSI phase bits do not match the value stored in
the
SCSI Status One (SSTAT1) register, the LSI53C896
generates a phase mismatch interrupt and the instruction
is not executed.
During a Message-Out phase, after the LSI53C896 has
performed a select with Attention (or SATN/ is manually
asserted with a Set ATN instruction), the LSI53C896
deasserts SATN/ during the final SREQ/SACK/ handshake.
When the LSI53C896 is performing a block move for
Message-In phase, it does not deassert the SACK/ signal
for the last SREQ/SACK/ handshake. Clear the
SACK/ signal using the Clear SACK I/O instruction.
OPC Instruction Defined
0 CHMOV/CHMOV64
1 MOVE/MOVE64