4 third dword, Figure5.14 memory move instructions – third dword, 7 load/store instructions – Avago Technologies LSI53C896 User Manual
Page 265: Third dword, Load/store instructions, Memory move instructions – third dword, Section 5.7, “load/store instructions
Load/Store Instructions
5-37
Version 3.3
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5.6.4 Third Dword
Figure 5.14 Memory Move Instructions – Third Dword
TEMP Register
[31:0]
These bits contain the destination address for the
Memory Move.
If the destination address is in the 64-bit address space,
the bits are contained in the
Memory Move Write Selector (MMWS)
register.
5.7 Load/Store Instructions
The Load/Store instructions provide a more efficient way to move data
from/to memory to/from an internal register in the chip without using the
normal memory move instruction.
The load/store instructions are represented by two-Dword opcodes. The
first Dword contains the
and
register values. The second Dword contains
the
DMA SCRIPTS Pointer Save (DSPS)
value. This is either the actual
memory location of where to load/store, or the offset from the
, depending on the value of bit 28
(DSA Relative).
For load operations where the data is read from the 64-bit address
space, the upper Dword of address resides in the
Memory Move Read Selector (MMRS)
register. For store operations
where the data is written to the 64-bit address space, the upper Dword
of address resides in the
Memory Move Write Selector (MMWS)
register.
A maximum of 4 bytes may be moved with these instructions. The
register address and memory address must have the same byte
alignment, and the count set such that it does not cross Dword
31
0
TEMP Register
31
0
MMWS Register