Nortel Networks 1000 - Manual (Page 979)

Architecture 979
The 1.5 Mb clock is generated by a Phase-Locked Loop (PLL). The PLL
synchronizes the 1.5 Mb DS1 clock to the 2.56 Mb system clock through
the common multiple of 8 kHz by using the main frame synchronization
signal.
Nortel Communication Server 1000
Circuit Card Reference
NN43001-311 02.06 Standard
27 August 2008
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