Chapter 11 ata controller – Freescale Semiconductor MPC5200B User Manual
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Table Of Contents
Paragraph
Page
Number
Number
MPC5200B Users Guide, Rev. 1
TOC-8
Freescale Semiconductor
10.4.6.2
Addressing ................................................................................................................................................10-57
10.4.6.3
Data Translation .......................................................................................................................................10-57
10.4.6.4
Initialization ..............................................................................................................................................10-57
10.4.6.5
Restart and Reset ......................................................................................................................................10-58
10.4.6.6
PCI Commands .........................................................................................................................................10-58
10.4.6.7
FIFO Considerations .................................................................................................................................10-58
10.4.6.8
Alarms ......................................................................................................................................................10-59
10.4.6.9
Bus Errors .................................................................................................................................................10-59
10.4.7
PCI - Supported Clock Ratios .........................................................................................................................10-59
10.4.8
Interrupts .........................................................................................................................................................10-59
10.4.8.1
PCI Bus Interrupts ....................................................................................................................................10-59
10.4.8.2
Internal Interrupt .......................................................................................................................................10-59
10.5
PCI Arbiter ............................................................................................................................................................10-59
10.6
Application Information ........................................................................................................................................10-60
10.6.1
XL bus Initiated Transaction Mapping ...........................................................................................................10-60
10.6.2
Address Maps ..................................................................................................................................................10-61
10.6.2.1
Address Translation ..................................................................................................................................10-61
10.6.2.1.1
Inbound Address Translation .............................................................................................................10-61
10.6.2.1.2
Outbound Address Translation ..........................................................................................................10-62
10.6.2.1.3
Base Address Register Overview .......................................................................................................10-63
10.6.3
XL bus Arbitration Priority .............................................................................................................................10-64
Chapter 11 ATA Controller
11.1
Overview .................................................................................................................................................................11-1
11.2
BestComm Key Features .........................................................................................................................................11-1
11.21
BestComm Read ...............................................................................................................................................11-1
11.2.2
BestComm Write ..............................................................................................................................................11-2
11.3
ATA Register Interface ...........................................................................................................................................11-2
11.3.1
ATA Host Registers—MBAR + 0x3A00 .........................................................................................................11-2
11.3.1.1
ATA Host Configuration Register—MBAR + 0x3A00 .............................................................................11-2
11.3.1.2
ATA Host Status Register—MBAR + 0x3A04 .........................................................................................11-3
11.3.1.3
ATA PIO Timing 1 Register—MBAR + 0x3A08 .....................................................................................11-3
11.3.1.4
ATA PIO Timing 2 Register—MBAR + 0x3A0C .....................................................................................11-4
11.3.1.5
ATA Multiword DMA Timing 1 Register—MBAR + 0x3A10 ................................................................11-4
11.3.1.6
ATA Multiword DMA Timing 2 Register—MBAR + 0x3A14 ................................................................11-5
11.3.1.7
ATA Ultra DMA Timing 1 Register—MBAR + 0x3A18 ..........................................................................11-5
11.3.1.8
ATA Ultra DMA Timing 2 Register—MBAR + 0x3A1C .........................................................................11-6
11.3.1.9
ATA Ultra DMA Timing 3 Register—MBAR + 0x3A20 .........................................................................11-6
11.3.1.10
ATA Ultra DMA Timing 4 Register—MBAR + 0x3A24 .........................................................................11-7
11.3.1.11
ATA Ultra DMA Timing 5 Register—MBAR + 0x3A28 .........................................................................11-8
11.3.1.12
ATA Share Count Register—MBAR + 0x3A2C .......................................................................................11-8
11.3.2
ATA FIFO Registers—MBAR + 0x3A00 ........................................................................................................11-8
11.3.2.1
ATA Rx/Tx FIFO Data Word Register—MBAR + 0x3A3C ....................................................................11-9
11.3.2.2
ATA Rx/Tx FIFO Status Register—MBAR + 0x3A40 ............................................................................11-9
11.3.2.3
ATA Rx/Tx FIFO Control Register—MBAR + 0x3A44 ........................................................................11-10
11.3.2.4
ATA Rx/Tx FIFO Alarm Register—MBAR + 0x3A48 ..........................................................................11-10
11.3.2.5
ATA Rx/Tx FIFO Read Pointer Register—MBAR + 0x3A4C ...............................................................11-11
11.3.2.6
ATA Rx/Tx FIFO Write Pointer Register—MBAR + 0x3A50 ..............................................................11-11
11.3.3
ATA Drive Registers—MBAR + 0x3A00 .....................................................................................................11-12
11.3.3.1
ATA Drive Device Control Register—MBAR + 0x3A5C ......................................................................11-12
11.3.3.2
ATA Drive Alternate Status Register—MBAR + 0x3A5C .....................................................................11-13
11.3.3.3
ATA Drive Data Register—MBAR + 0x3A60 ........................................................................................11-13
11.3.3.4
ATA Drive Features Register—MBAR + 0x3A64 ..................................................................................11-14