3 ata rx / tx fifo control register-mbar + 0x3a44, 4 ata rx / tx fifo alarm register-mbar + 0x3a48, Ata rx/tx fifo alarm register – Freescale Semiconductor MPC5200B User Manual
Page 375: Ata rx/tx fifo control register
MPC5200B Users Guide, Rev. 1
11-10
Freescale Semiconductor
ATA Register Interface
11.3.2.3
ATA Rx/Tx FIFO Control Register—MBAR + 0x3A44
11.3.2.4
ATA Rx/Tx FIFO Alarm Register—MBAR + 0x3A48
10
UF
UnderFlow—flag indicates read pointer has surpassed the write pointer. FIFO was read
beyond empty. Resetting FIFO clears this condition; writing 1 to this bit clears flag.
11
OF
OverFlow—flag indicates write pointer surpassed read pointer. FIFO was written beyond full.
Resetting FIFO clears this condition; writing 1 to this bit clears flag.
12
Full
FIFO full—this is NOT a sticky bit or error condition. Full indication tracks with FIFO state.
13
HI
High—FIFO requests attention, because high level alarm is asserted. To clear this condition,
FIFO must be read to a level below the setting in granularity bits.
14
LO
Low—FIFO requests attention, because Low level alarm is asserted. To clear this condition,
FIFO must be written to a level in which the space remaining is less than the granularity bit
setting.
15
Emty
FIFO empty—this is NOT a sticky bit or error condition. Full indication tracks with FIFO state.
16:31
—
Reserved
Table 11-15. ATA Rx/Tx FIFO Control Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
WFR
Reserved
GR
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:1
—
Reserved
2
WFR
Write End of Frame (EOF) This bit should remain low.
3:4
—
Reserved
5:7
GR
Granularity—bits control high “watermark” point at which FIFO negates Alarm condition (i.e.,
request for data). It represents the number of free bytes times 4.
000 = FIFO waits to become completely full before stopping data request.
001 = FIFO stops data request when only one long word of space remains.
8:31
—
Reserved
Table 11-16. ATA Rx/Tx FIFO Alarm Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description