Freescale Semiconductor MPC5200B - Manual (Page 266)

Overview
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 9-1
Chapter 9
LocalPlus Bus (External Bus Interface)
9.1 Overview
The LocalPlus Bus is the external bus interface of the MPC5200B. This multi-function bus system supports interfacing to external Boot ROM
or Flash memories, external SRAM memories or other memory mapped devices. The following sections are contained herein:
• Section 9.1, Overview
• Section 9.2, Features
• Section 9.3, Interface
— Section 9.3.1, External Signals
— Section 9.3.2, Block Diagram
• Section 9.4, Modes of Operation
— Section 9.4.1, Non-MUXed Mode
— Section 9.4.2, MUXed Mode
• Section 9.5, Configuration
— Section 9.5.1, Boot Configuration
— Section 9.5.2, Chip Selects Configuration
— Section 9.5.3, Reset Configuration
• Section 9.6, DMA (BestComm) Interface (SCLPC)
• Section 9.7, Programmer’s Model
— Section 9.7.1, Interrupt and Bus Errors
— Section 9.7.1, Chip Select/LPC Registers—MBAR + 0x0300
— Section 9.7.2, SCLPC Registers—MBAR + 0x3C00
— Section 9.7.3, SCLPC FIFO Registers—MBAR + 0x3C40
The MPC5200B offers a shared external 32-bit address/data bus, which supports connections to PCI and ATA compliant devices, as well as
memory mapped devices such as Flash memories, ROM, SRAM, gate-array logic, or other simple target (slave) devices with little or no
additional circuitry. Separate control signals are used by each interface. The on-chip arbiter (called PCI Arbiter) controls the access to the
shared AD bus for the different clients.
NOTE
If the PCI interface is NOT used (and internally disabled) the PCI control pins must be terminated as
indicated by the PCI Local Bus specification. PCI control signals always require pull-up resistors on
the motherboard (not the expansion board) to ensure that they contain stable values when no agent is
actively driving the bus. This includes PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL,
PCI_STOP, PCI_SERR, PCI_PERR, and PCI_REQ.
The PCI signals, which are not used as address in Large Flash mode, are drive low during a Large
Flash access. This includes PCI_SERR, PCI_PERR, PCI_IDSEL, PCI_REQ, PCI_GNT and
PCI_RESET.
The PCI interface is described in Chapter 10, PCI Controller . The ATA compliant interface is described in Chapter 11, ATA Controller . The
interface for memory mapped devices, called LocalPlus Bus, is described in this chapter. The MPC5200B LocalPlus Controller (LPC) module
implements the LocalPlus Bus interface.
The LocalPlus Bus interface provides a high flexibility and all its different operating modes can be selected by means of software
configuration and in some cases minimal external logic (in multiplexed mode).
9.2 Features
LocalPlus has the following features:
• Interface to memory mapped or chip selected devices
• Two main modes of operation :
— non-MUXed Modes
Legacy Modes (Address 8, 16, or 24 bits, Data 8 or 16 bits)
Most Graphics Mode (Address 24 bits, Data 32 bits)
Large Flash Mode (Address 26 bits, Data 8 or 16 bits)
— MUXed Modes