2 architecture, Architecture -2 – Freescale Semiconductor MPC5200B User Manual

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MPC5200B Users Guide, Rev. 1

1-2

Freescale Semiconductor

Architecture

— IrDA mode from 2400 bps to 4 Mbps

•

Fast Ethernet Controller (FEC)
— Supports 100Mbps IEEE 802.3 MII, 10Mbps IEEE 802.3 MII, 10Mbps 7-wire interface

•

Universal Serial Bus Controller (USB)
— USB Revision 1.1 Host
— Open Host Controller Interface (OHCI)
— Integrated USB Hub, with two ports.

•

Two Inter-Integrated Circuit Interfaces (I

•

Serial Peripheral Interface (SPI)

•

Dual CAN 2.0 A/B Controller (MSCAN)
— Motorola Scalable CAN (MSCAN) architecture
— Implementation of version 2.0A/B CAN protocol
— Standard and extended data frames

•

J1850 Byte Data Link Controller (BDLC)
— J1850 Class B data communication network interface compatible and ISO compatible for low speed (<125kbps) serial data

communications in automotive applications.

— Supports 4X mode, 41.6 kbps
— In-frame response (IFR) types 0, 1, 2, and 3 supported

•

Systems level features
— Interrupt Controller supports 4 external interrupt request lines and 47 internal interrupt sources
— GPIO/Timer functions

– Up to 56 total GPIO pins (depending on functional multiplexing selections) that support a variety of interrupt/Wake Up

capabilities.

– 8 GPIO pins with timer capability supporting input capture, output compare and pulse width modulation (PWM) functions

— Real-time Clock with 1 second resolution
— Systems Protection (watch dog timer, bus monitor)
— Individual control of functional block clock sources
— Power management: Nap, Doze, Sleep, Deep Sleep modes
— Support of Wake Up from low power modes by different sources (GPIO, RTC, CAN)

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Test/Debug features
— JTAG (IEEE 1149.1 test access port)
— Common On-Chip Processor (COP) debug port

•

On-board PLL and clock generation

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Software
— QNX
— VXWorks
— Linux
— Software Modem capable
— JAVA

1.2

Architecture

The following areas comprise the MPC5200B system architecture:

•

Embedded e300 Core

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