Freescale Semiconductor MPC5200B - Manual (Page 344)

Functional Description
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 10-47
Figure 10-3. PCI Write Terminated by Target
10.4.1.4 PCI Bus Commands
PCI supports a number of different commands. These commands are presented by the initiator on the C/BE[3:0] lines during the address phase
of a PCI transaction.
Table 10-5. PCI Bus Commands
C/BE[3:0]
PCI Bus
Command
MPC5200B
supports as
Initiator
MPC5200B
supports
as Target
Definition
0000 Interrupt
Acknowledge
Yes No The interrupt acknowledge command is a read
(implicitly addressing an external interrupt
controller). Only one device on the PCI bus should
respond to the interrupt acknowledge command.
0001 Special Cycle Yes No The Special Cycle command provides a
mechanism to broadcast select messages to all
devices on the PCI bus.
0010 I/O-read Yes No The I/O-read command accesses agents mapped
into the PCI I/O space.
0011 I/O-write Yes No The I/O-write command accesses agents mapped
into the PCI I/O space.
0100 Reserved No No --
0101 Reserved No No --
0110 Memory-read Yes Yes The memory read command accesses agents
mapped into PCI memory space.
A1 D1 D2
1 2 3 4 5 6 7 8
CMD Byte Enables
Address
Phase
Data Phase 1 Data Phase 2
STOP
CLK
FRAME
C/BE
IRDY
TRDY
DEVSEL
AD
(wait)