Freescale Semiconductor MPC5200B - Manual (Page 6)

Table of Contents
Paragraph Page
Number Number
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor TOC-5
8.4.4.3 Bank Active Command ..............................................................................................................................8-14
8.4.4.4 Read Command ..........................................................................................................................................8-14
8.4.4.5 Write Command .........................................................................................................................................8-14
8.4.4.6 Auto Refresh Command .............................................................................................................................8-15
8.4.4.7 Self Refresh and Power Down Commands ................................................................................................8-15
8.5 Operation .................................................................................................................................................................8-15
8.5.1 Power-Up Initialization .....................................................................................................................................8-15
8.5.2 Read Clock ........................................................................................................................................................8-16
8.5.2.1 Read Clock Programming Algorithm .........................................................................................................8-16
8.6 Programming the SDRAM Controller ....................................................................................................................8-17
8.7 Memory Controller Registers (MBAR+0x0100:0x010C) ......................................................................................8-18
8.7.1 Mode Register—MBAR + 0x0100 ...................................................................................................................8-18
8.7.2 Control Register—MBAR + 0x0104 ................................................................................................................8-19
8.7.3 Configuration Register 1—MBAR + 0x0108 ...................................................................................................8-21
8.7.4 Configuration Register 2—MBAR + 0x010C ..................................................................................................8-23
8.8 Address Bus Mapping .............................................................................................................................................8-25
8.8.1 Example—Physical Address Multiplexing .......................................................................................................8-25
Chapter 9 LocalPlus Bus (External Bus Interface)
9.1 Overview ...................................................................................................................................................................9-1
9.2 Features .....................................................................................................................................................................9-1
9.3 Interface .....................................................................................................................................................................9-2
9.3.1 External Signals ..................................................................................................................................................9-2
9.3.2 Block Diagram .....................................................................................................................................................v2
9.4 Modes of Operation ...................................................................................................................................................9-4
9.4.1 Non-MUXed Mode .............................................................................................................................................9-4
9.4.2 MUXed Mode .....................................................................................................................................................9-6
9.4.2.1 Address Tenure .............................................................................................................................................9-7
9.4.2.2 Data Tenure ..................................................................................................................................................9-8
9.5 Configuration .............................................................................................................................................................9-9
9.5.1 Boot Configuration .............................................................................................................................................9-9
9.5.2 Chip Selects Configuration ...............................................................................................................................9-10
9.5.3 Reset Configuration ..........................................................................................................................................9-10
9.6 DMA (BestComm) Interface (SCLPC) ...................................................................................................................9-11
9.7 Programmer’s Model ...............................................................................................................................................9-11
9.7.1 Interrupt and Bus Errors ....................................................................................................................................9-11
9.7.2 Chip Select/LPC Registers—MBAR + 0x0300 ...............................................................................................9-12
9.7.2.1 Chip Select 0/Boot Configuration Register—MBAR + 0x0300 ................................................................9-13
9.7.2.2 Chip Select 1 Configuration Register—MBAR + 0x0304......................................................................... 9-15
9.7.2.3 Chip Select Control Register—MBAR + 0x0318 ...................................................................................... 9-17
9.7.2.4 Chip Select Status Register—MBAR + 0x031C........................................................................................ 9-18
9.7.2.5 Chip Select Burst Control Register—MBAR + 0x0328 ............................................................................9-19
9.7.2.6 Chip Select Deadcycle Control Register—MBAR + 0x032C ................................................................... 9-22
9.7.3 SCLPC Registers—MBAR + 0x3C00.............................................................................................................. 9-23
9.7.3.1 SCLPC Packet Size Register—MBAR + 0x3C00 ..................................................................................... 9-23
9.7.3.2 SCLPC Start Address Register—MBAR + 0x3C04 ..................................................................................9-24
9.7.3.3 SCLPC Control Register—MBAR + 0x3C08 ............................................................................................9-25
9.7.3.4 SCLPC Enable Register—MBAR + 0x3C0C ............................................................................................9-26
9.7.3.5 SCLPC Bytes Done Status Register—MBAR + 0x3C14 ..........................................................................9-27
9.7.4 SCLPC FIFO Registers—MBAR + 0x3C40 ....................................................................................................9-27
9.7.4.1 LPC Rx/Tx FIFO Data Word Register—MBAR + 0x3C40 ......................................................................9-28
9.7.4.2 LPC Rx/Tx FIFO Status Register—MBAR + 0x3C44 .............................................................................9-28
9.7.4.3 LPC Rx/Tx FIFO Control Register—MBAR + 0x3C48 ...........................................................................9-29