Freescale Semiconductor MPC5200B - Manual (Page 12)

Table of Contents
Paragraph Page
Number Number
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor TOC-11
13.12.22 SDMA Initiator Priority 24 Register—MBAR + 0x1254 ...............................................................................13-17
13.12.23 SDMA Initiator Priority 28 Register—MBAR + 0x1258 ...............................................................................13-18
13.12.24 SDMA Requestor MuxControl—MBAR + 0x125C ......................................................................................13-19
13.12.25 SDMA task Size0—MBAR + 0x1260 ............................................................................................................13-21
13.12.26 SDMA task 0 & task Size 1 map ....................................................................................................................13-21
13.12.27 SDMA Reserved Register 1—MBAR + 0x1268 ............................................................................................13-22
13.12.28 SDMA Reserved Register 2—MBAR + 0x126C ...........................................................................................13-22
13.12.29 SDMA Debug Module Comparator 1, Value1 Register—MBAR + 0x1270 .................................................13-22
13.12.30 SDMA Debug Module Comparator 2, Value2 Register—MBAR + 0x1274 .................................................13-23
13.12.31 SDMA Debug Module Control Register—MBAR + 0x1278 ........................................................................13-23
13.12.32 SDMA Debug Module Status Register—MBAR + 0x127C ..........................................................................13-25
13.13 On-Chip SRAM .....................................................................................................................................................13-26
13.14 Programming Model ..............................................................................................................................................13-26
13.14.1 Task Table .......................................................................................................................................................13-26
13.14.1.1 Integer Mode .............................................................................................................................................13-28
13.14.1.2 Pack ..........................................................................................................................................................13-28
13.14.2 Variable Table .................................................................................................................................................13-28
Chapter 14 Fast Ethernet Controller (FEC)
14.1 Overview .................................................................................................................................................................14-1
14.1.1 Features .............................................................................................................................................................14-2
14.2 Modes of Operation .................................................................................................................................................14-3
14.2.1 Full- and Half-Duplex Operation ......................................................................................................................14-3
14.2.2 10Mbps and 100Mbps MII Interface Operation ...............................................................................................14-3
14.2.3 10Mbps 7-Wire Interface Operation .................................................................................................................14-3
14.2.4 Address Recognition Options ...........................................................................................................................14-3
14.2.5 Internal Loopback .............................................................................................................................................14-3
14.3 I/O Signal Overview ...............................................................................................................................................14-3
14.3.1 Detailed Signal Descriptions .............................................................................................................................14-4
14.3.1.1 MII Ethernet MAC-PHY Interface .............................................................................................................14-4
14.3.1.2 MII Management Frame Structure .............................................................................................................14-5
14.3.1.2.1 MII Management Register Set .............................................................................................................14-6
14.4 FEC Memory Map and Registers ............................................................................................................................14-6
14.4.1 Top Level Module Memory Map .....................................................................................................................14-7
14.4.2 Control and Status (CSR) Memory Map ..........................................................................................................14-7
14.4.3 MIB Block Counters Memory Map ..................................................................................................................14-8
14.5 FEC Registers—MBAR + 0x3000 ........................................................................................................................14-10
14.5.1 FEC ID Register—MBAR + 0x3000 ..............................................................................................................14-11
14.5.2 FEC Interrupt Event Register—MBAR + 0x3004 ..........................................................................................14-12
14.5.3 FEC Interrupt Enable Register—MBAR + 0x3008 ........................................................................................14-14
14.5.4 FEC Rx Descriptor Active Register—MBAR + 0x3010 ................................................................................14-14
14.5.5 FEC Tx Descriptor Active Register—MBAR + 0x3014 ................................................................................14-15
14.5.6 FEC Ethernet Control Register—MBAR + 0x3024 .......................................................................................14-16
14.5.7 FEC MII Management Frame Register—MBAR + 0x3040 ...........................................................................14-17
14.5.8 FEC MII Speed Control Register—MBAR + 0x3044 ....................................................................................14-18
14.5.9 FEC MIB Control Register—MBAR + 0x3064 .............................................................................................14-19
14.5.10 FEC Receive Control Register—MBAR + 0x3084 ........................................................................................14-20
14.5.11 FEC Hash Register—MBAR + 0x3088 ..........................................................................................................14-21
14.5.12 FEC Tx Control Register—MBAR + 0x30C4 ................................................................................................14-21
14.5.13 FEC Physical Address Low Register—MBAR + 0x30E4 .............................................................................14-22
14.5.14 FEC Physical Address High Register—MBAR + 0x30E8 .............................................................................14-23
14.5.15 FEC Opcode/Pause Duration Register—MBAR + 0x30EC ..........................................................................14-23
14.5.16 FEC Descriptor Individual Address 1 Registe—MBAR + 0x3118 ................................................................14-24