Freescale Semiconductor MPC5200B - Manual (Page 514)

Overview
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 15-3
PSC detect a “codec not ready” status the PSC will stop sending and receiving data. In the enhanced AC97 mode, only the data
slots must be in the FIFO. The PSC generate the slot0,1 and slot2 values depend on data to send. In both AC97 modes the PSC
reads only 32 bits from the FIFO. For more information about the AC97 mode see
Section 15.3.3, PSC in AC97 Mode
3. PSC UART mode: When programmed as a UART the PSC serial communication channel provides a full-duplex asynchronous
receiver and transmitter deriving an operating frequency from an internal clock. The transmitter converts parallel data from the
CPU to a serial bit-stream, inserting appropriate start, stop, and parity bits. It outputs the resulting stream on the channel
transmitter serial data output (TxD). The receiver converts serial data from the channel receiver serial data input (RxD) to parallel
format, checks for start, stop, and parity bits, or line break conditions, and transfers the assembled character onto the bus during
read operations. The receiver may be poll-driven or interrupt-driven. For more information about the UART mode see section:
Section 15.3.1, PSC in UART Mode .
4. PSC IrDA mode: When programmed as an IrDA interface the PSC provides an full-duplex asynchronous communication which is
optimized for Infrared transmission. The in this configuration the SIR, MIR and FIR modes are supported. The transmitter
converts the parallel data from the CPU to a serial bit-stream and add some control characters, the receiver checks the control
characters and converts the serial data from the RX line to parallel data. For more information about the UART mode see section:
Section 15.3.4, PSC in IrDA mode .
15.1.2 Features
General Features:
• 512-byte receiver (Rx) FIFO
• 512-byte transmitter (Tx) FIFO
• Each channel is programmable to normal (full-duplex), automatic echo, local loop-back, or remote loop-back mode
• Automatic Walk-up mode for multidrop applications
• 6 maskable interrupt conditions
• PSC Tx and Rx FIFOs can be programmed to interrupt either the BestComm or the CPU when they require filling or emptying,
respectively.
PSC UART mode:
• Each is clocked by an internal clock source (IPB clock), eliminating the need for an external crystal
• Full-duplex asynchronous receiver/transmitter channel
• Programmable data format:
— five to eight data bits plus parity
— Odd, even, no parity, or force parity
— One, one-and-a-half, or two STOP bits
• Parity, framing, and overrun error detection
• False-start bit detection
• Line-break detection and generation
• Detection of breaks originating in the middle of a character
• Start/end break interrupt/status
PSC Codec mode:
• Programmable to interface to an 8, 16, 24 or 32bit Codec for “soft modem” support
• Support master mode, driving clock and FrameSync signals
• Support slave mode, receiving clock and the FrameSync from the external Codec
• Supports full duplex SPI interface
• Supports I2S interface
• No parity error, framing error, or line break detection in Codec mode
• Ability to generate a master clock (Mclk) for an external Codec device, independent from the mode (master or slave)
• Programmable width of the FrameSync signal
• FrameSync and bit clock frequencies are independently programmable
• Frame sync and bit clock polarity are programmable
• Support “digital cell phone” interface
AC97 mode:
• PSC1 and PSC2 support an AC97 interface
IrDA SIR mode:
• Baud rate: 2400 to 115200 bps