Freescale Semiconductor MPC5200B - Manual (Page 294)

Programmer’s Model
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 9-29
9.7.3.2 LPC Rx/Tx FIFO Status Register—MBAR + 0x3C44
Bits Name Description
0:31 FIFO_Data_Word The FIFO data port. Reading from this location “pops” data from the FIFO, writing
“pushes” data into the FIFO. During normal operation the BestComm Controller
pushes data here.
Note: ONLY full word access is allowed. If all byte enables are not asserted when
accessing this location, a FIFO error flag is generated.
Table 9-19. LPC Rx/Tx FIFO Status Register
msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R Reserved Err UF OF Full HI LO Emty
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R Reserved
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
0:8 — Reserved
9 Err Error—flag bit is essentially the logical "OR" of other flag bits and can be polled for detection
of any FIFO error. After clearing the offending condition, writing 1 to this bit clears flag.
10 UF UnderFlow—flag indicates read pointer has surpassed the write pointer. FIFO was read
beyond empty. Resetting FIFO clears this condition; writing 1 to this bit clears flag.
11 OF OverFlow—flag indicates write pointer surpassed read pointer. FIFO was written beyond full.
Resetting FIFO clears this condition; writing 1 to this bit clears flag.
12 Full FIFO full—this is NOT a sticky bit or error condition. Full indication tracks with FIFO state.
13 HI High—FIFO requests attention, because high level alarm is asserted. To clear this condition,
FIFO must be read to a level below the setting in granularity bits.
14 LO Low—FIFO requests attention, because Low level alarm is asserted. To clear this condition,
FIFO must be written to a level in which the space remaining is less than the granularity bit
setting.
15 Emty FIFO empty—this is NOT a sticky bit or error condition. Full indication tracks with FIFO state.
16:31 — Reserved