Freescale Semiconductor MPC5200B - Manual (Page 759)

MPC5200B Users Guide, Rev. 1
B-8 Freescale Semiconductor
15.2.43 Tx FIFO Write Pointer (0x96)—TFWPTR ........................................................................................ 15-43
15.2.44 Tx FIFO Last Read Frame (0x9A)—TFLRFPTR .............................................................................. 15-43
15.2.45 Tx FIFO Last Write Frame PTR (0x9C)—TFLWFPTR..................................................................... 15-43
Section 16.2 XLB Arbiter Registers—MBAR + 0x1F00 ............................................................................................... 16-3
16.2.1 Arbiter Configuration Register (R/W)—MBAR + 0x1F40.................................................................. 16-3
16.2.2 Arbiter Version Register (R)—MBAR + 0x1F44................................................................................. 16-5
16.2.3 Arbiter Status Register (R/W)—MBAR + 0x1F48 .............................................................................. 16-5
16.2.4 Arbiter Interrupt Enable Register (R/W)—MBAR + 0x1F4C ............................................................. 16-6
16.2.5 Arbiter Address Capture Register (R)—MBAR + 0x1F50 .................................................................. 16-7
16.2.6 Arbiter Bus Signal Capture Register (R)—MBAR + 0x1F54.............................................................. 16-8
16.2.7 Arbiter Address Tenure Time-Out Register (R/W)—MBAR + 0x1F58 .............................................. 16-8
16.2.8 Arbiter Data Tenure Time-Out Register (R/W)—MBAR + 0x1F5C ................................................... 16-9
16.2.9 Arbiter Bus Activity Time-Out Register (R/W)—MBAR + 0x1F60 ................................................... 16-9
16.2.10 Arbiter Master Priority Enable Register (R/W)—MBAR + 0x1F64.................................................. 16-10
16.2.11 Arbiter Master Priority Register (R/W)—MBAR + 0x1F68...............................................................16-11
16.2.12 Arbiter Snoop Window Register (RW)—MBAR + 0x1F70 .............................................................. 16-12
16.2.13 Arbiter Reserved Registers—MBAR + 0x1F00-1F3C, 0x1F74-1FFF .............................................. 16-13
Section 17.3 SPI Registers—MBAR + 0x0F00 .............................................................................................................. 17-3
17.3.1 SPI Control Register 1—MBAR + 0x0F00.......................................................................................... 17-3
17.3.2 SPI Control Register 2—MBAR + 0x0F01.......................................................................................... 17-4
17.3.3 SPI Baud Rate Register—MBAR + 0x0F04 ........................................................................................ 17-5
17.3.4 SPI Status Register —MBAR + 0x0F05 .............................................................................................. 17-6
17.3.5 SPI Data Register—MBAR + 0x0F09 ................................................................................................. 17-7
17.3.6 SPI Port Data Register—MBAR + 0x0F0D......................................................................................... 17-7
17.3.7 SPI Data Direction Register—MBAR + 0x0F10 ................................................................................. 17-7
Section 18.3 I
2
C Interface Registers ............................................................................................................................... 18-5
18.3.1 I2C Address Register (MADR)—MBAR + 0x3D00 / 0x3D40 ........................................................... 18-6
18.3.2 I2C Frequency Divider Register (MFDR)—MBAR + 0x3D04 / 0x3D44 ........................................... 18-6
18.3.3 I2C Control Register (MCR)—MBAR + 0x3D08 / 0x3D48 ............................................................. 18-13
18.3.4 I2C Status Register (MSR)—MBAR + 0x3D0C / 0x3D4C............................................................... 18-15
18.3.5 I2C Data I/O Register (MDR)—MBAR+ x3D10 / 0x3D50.............................................................. 18-16
18.3.6 I2C Interrupt Control Register—MBAR + 0x3D20........................................................................... 18-17
18.3.7 I2C Filter Register (MIFR)—MBAR + 0x3D24 ................................................................................ 18-18
Section 19.5 Memory Map / Register Definition ............................................................................................................ 19-3
19.5.2 Register Descriptions............................................................................................................................ 19-5
19.5.3 MSCAN Control Register 0 (CANCTL0)—MBAR + 0x0900 / 0x980............................................... 19-5
19.5.4 MSCAN Control Register 1 (CANCTL1)—MBAR + 0x0901 / 0x981............................................... 19-7
19.5.5 MSCAN Bus Timing Register 0 (CANBTR0)—MBAR + 0x0904 / 0x984........................................ 19-8
19.5.6 MSCAN Bus Timing Register 1 (CANBTR1)—MBAR + 0x0905 / 0x985........................................ 19-9
19.5.7 MSCAN Receiver Flag Register (CANRFLG)—MBAR+0x0908 / 0x988 ....................................... 19-10
19.5.8 MSCAN Receiver Interrupt Enable Register (CANRIER)—MBAR + 0x0909 / 0x989 ................... 19-12
19.5.9 MSCAN Transmitter Flag Register (CANTFLG)—MBAR + 0x090C / 0x98C................................ 19-13
19.5.10 MSCAN Transmitter Interrupt Enable Register (CANTIER)—MBAR+0x090D / 0x098D ............. 19-14
19.5.11 MSCAN Transmitter Message Abort Request (CANTARQ)—MBAR + 0x0910 / 0x0990.............. 19-14
19.5.12 MSCAN Transmitter Message Abort Ack (CANTAAK)—MBAR +0x0911 / 0x0991..................... 19-15
19.5.13 MSCAN Transmit Buffer Selection (CANTBSEL)—MBAR + 0x0914 /0x0991 ............................. 19-15
19.5.14 MSCAN ID Acceptance Control Register (CANIDAC)—MBAR + 0x0915 / 0x0995..................... 19-16
19.5.15 MSCAN Receive Error Counter Register (CANRXERR)-MBAR + 0x091C / 0x099C ................... 19-17