Freescale Semiconductor MPC5200B - Manual (Page 8)

Table of Contents
Paragraph Page
Number Number
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor TOC-7
10.3.3.1.4 Tx Enables PCITER(RW)—MBAR + 0x380C .................................................................................10-24
10.3.3.1.5 Tx Next Address PCITNAR(R) —MBAR + 0x3810 ........................................................................10-25
10.3.3.1.6 Tx Last Word PCITLWR(R) —MBAR + 0x3814 ............................................................................10-26
10.3.3.1.7 Tx Done Counts PCITDCR(R) —MBAR + 0x3818 .........................................................................10-26
10.3.3.1.8 Tx Status PCITSR(RWC) —MBAR + 0x381C .................................................................................10-27
10.3.3.1.9 Tx FIFO Data Register PCITFDR(RW) —MBAR + 0x3840 ...........................................................10-28
10.3.3.1.10 Tx FIFO Status Register PCITFSR(R/RWC) —MBAR + 0x3844 ...................................................10-28
10.3.3.1.11 Tx FIFO Control Register PCITFCR(RW) —MBAR + 0x3848 .......................................................10-29
10.3.3.1.12 Tx FIFO Alarm Register PCITFAR(RW) —MBAR + 0x384C ........................................................10-30
10.3.3.1.13 Tx FIFO Read Pointer Register PCITFRPR(RW) —MBAR + 0x3850 ............................................10-31
10.3.3.1.14 Tx FIFO Write Pointer Register PCITFWPR(RW) —MBAR + 0x3854 ..........................................10-31
10.3.3.2 Multi-Channel DMA Receive Interface ...................................................................................................10-31
10.3.3.2.1 Rx Packet Size PCIRPSR(RW) —MBAR + 0x3880 ........................................................................10-32
10.3.3.2.2 Rx Start Address PCIRSAR (RW)—MBAR + 0x3884 .....................................................................10-32
10.3.3.2.3 Rx Transaction Control Register PCIRTCR(RW) —MBAR + 0x3888 ............................................10-32
10.3.3.2.4 Rx Enables PCIRER (RW) —MBAR + 0x388C ...............................................................................10-34
10.3.3.2.5 Rx Next Address PCIRNAR(R) —MBAR + 0x3890 ........................................................................10-35
10.3.3.2.6 Rx Last Word PCIRLWR(R) —MBAR + 0x3894 ............................................................................10-35
10.3.3.2.7 RxDone Counts PCIRDCR(R) —MBAR + 0x3898 ..........................................................................10-36
10.3.3.2.8 Rx Status PCIRSR (R/sw1) —MBAR + 0x389C ..............................................................................10-36
10.3.3.2.9 Rx FIFO Data Register PCIRFDR(RW) —MBAR + 0x38C0 ..........................................................10-38
10.3.3.2.10 Rx FIFO Status Register PCIRFSR(R/sw1) —MBAR + 0x38C4 .....................................................10-38
10.3.3.2.11 Rx FIFO Control Register PCIRFCR(RW) —MBAR + 0x38C8 ......................................................10-39
10.3.3.2.12 Rx FIFO Alarm Register PCIRFAR(RW) —MBAR + 0x38CC .......................................................10-40
10.3.3.2.13 Rx FIFO Read Pointer Register PCIRFRPR(RW) —MBAR + 0x38D0 ...........................................10-40
10.3.3.2.14 Rx FIFO Write Pointer Register PCIRFWPR (RW) —MBAR + 0x38D4 ........................................10-41
10.4 Functional Description ..........................................................................................................................................10-41
10.4.1 PCI Bus Protocol .............................................................................................................................................10-41
10.4.1.1 PCI Bus Background ................................................................................................................................10-41
10.4.1.2 Basic Transfer Control ..............................................................................................................................10-42
10.4.1.3 PCI Transactions .......................................................................................................................................10-42
10.4.1.4 PCI Bus Commands ..................................................................................................................................10-44
10.4.1.5 Addressing ................................................................................................................................................10-45
10.4.1.5.1 Memory space addressing ..................................................................................................................10-45
10.4.1.5.2 I/O space addressing ..........................................................................................................................10-46
10.4.1.5.3 Configuration space addressing and transactions ..............................................................................10-46
10.4.1.5.4 Address decoding ...............................................................................................................................10-47
10.4.2 Initiator Arbitration .........................................................................................................................................10-48
10.4.2.1 Priority Scheme ........................................................................................................................................10-48
10.4.3 Configuration Interface ...................................................................................................................................10-48
10.4.4 XL bus Initiator Interface ................................................................................................................................10-48
10.4.4.1 Endian Translation ....................................................................................................................................10-49
10.4.4.2 Configuration Mechanism ........................................................................................................................10-51
10.4.4.2.1 Type 0 Configuration Translation ......................................................................................................10-51
10.4.4.2.2 Type 1 Configuration Translation ......................................................................................................10-53
10.4.4.2.3 Interrupt Acknowledge Transactions .................................................................................................10-53
10.4.4.2.4 Special Cycle Transactions ................................................................................................................10-53
10.4.4.3 Transaction Termination ...........................................................................................................................10-54
10.4.5 XL bus Target Interface .................................................................................................................................10-54
10.4.5.1 Reads from Local Memory .......................................................................................................................10-55
10.4.5.2 Local Memory Writes ...............................................................................................................................10-55
10.4.5.3 Data Translation .......................................................................................................................................10-55
10.4.5.4 Target Abort .............................................................................................................................................10-56
10.4.5.5 Latrule Disable .........................................................................................................................................10-56
10.4.6 Communication Sub-System Initiator Interface .............................................................................................10-56
10.4.6.1 Access Width ............................................................................................................................................10-57