Freescale Semiconductor MPC5200B - Manual (Page 44)

Architecture
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 1-9
A Wake Up capability is supported by CAN, RTC, several GPIOs and the interrupt lines. Therefore, the MPC5200B can be shut down to a
low-power standby mode, then re-enabled by one of the Wake Up inputs without resetting the MPC5200B.
1.2.9 Systems Debug and Test
The MPC5200B supports the Common On-chip Processor (COP) debug capability common on other microprocessors that use the PowerPC
architecture. The COP interface supports features such as:
• memory down load
• single step instruction execution
• break/watch point capability
• access to internal registers
• pipeline tracking, etc.
The MPC5200B also supports a JTAG IEEE 1149.1 controller and test access port (TAP).
1.2.10 Physical Characteristics
• 1.5V internal, 3.3V external operation (2.5v for DDR interface)
• TTL compatible I/O pins
• 272-pin Plastic Ball Grid Array (PBGA)