3 processor bus (xlb ) clock domain, 4 sdram memory controller clock domain, Processor bus (xlb ) clock domain – Freescale Semiconductor MPC5200B User Manual

Page 140: Sdram memory controller clock domain

MPC5200B Clock Domains

MPC5200B Users Guide, Rev. 1

Freescale Semiconductor

5-7

NOTE

The XLB CLOCK frequency and the ppc_pll_cfg[0:4] must be chosen such that resulting CORE
CLOCK frequency and PLL (f

VCOcore

) frequency do not exceed their respective maximium or

minimum operating frequencies. Refer to

Table 5-5

and MPC5200B Hareware Specification.

5.3.3

Processor Bus (XLB ) Clock Domain

The XLB clock (xlb_clk) is the fundamental MPC5200B clock frequency. The following operate at this frequency:

•

The internal processor address/data bus

•

The internal SDRAM Controller

•

External SDRAM

All functional blocks that interface to the XLB must operate at this frequency, or have a section of logic that operates at this frequency.

5.3.4

SDRAM Memory Controller Clock Domain

The Memory Controller uses the clocks shown in

Table 5-7

0x08

01000

1:3

1:2

1:6

0x09

01001

1:5.5

1:2

1:11

0x0A

01010

1:4

1:2

1:8

0x0B

01011

1:5

1:2

1:10

0x0C

01100

—

0x0D

01101

1:6

1:2

1:12

0x0E

01110

1:3.5

1:2

1:7

0x10

10000

1:3

1:4