List of figures – Freescale Semiconductor MPC5200B User Manual
Page 20
List of Figures
Figure
Page
Number
Number
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
LOF-1
2-1
272-Pin PBGA Pin Detail ..........................................................................................................................................2-2
2-2
272-Pin PBGA — Top View .....................................................................................................................................2-3
2-3
MPC5200 Peripheral Muxing ...................................................................................................................................2-4
2-4
PSC1 Port Map—5 Pins ..........................................................................................................................................2-31
2-5
PSC2 Port Map—5 Pins ..........................................................................................................................................2-34
2-6
PSC3 Port Map—10 Pins ........................................................................................................................................2-37
2-7
USB Port Map—10 Pins .........................................................................................................................................2-43
2-8
Ethernet Output Port Map—8 Pins .........................................................................................................................2-46
2-9
Ethernet Input / Control Port Map—10 Pins ..........................................................................................................2-47
2-10
Timer Port Map—8 Pins .........................................................................................................................................2-62
2-11
PSC6 Port Map—4 Pins ..........................................................................................................................................2-65
2-12
I
2
C Port Map—4 Pins (two pins each, for two I
2
Cs) .............................................................................................2-67
4-1
Reset sequence ..........................................................................................................................................................4-2
4-2
PORESET Assertion .................................................................................................................................................4-3
4-3
Internal Hard Reset vs External HRESET Assertion ................................................................................................4-3
5-1
Primary Synchronous Clock Domains ......................................................................................................................5-2
5-2
MPC5200 Clock Relations ........................................................................................................................................5-3
5-3
Timing Diagram—Clock Waveforms for SDRAM and DDR Memories .................................................................5-8
7-1
Interrupt Sources and Core Interrupt Pins .................................................................................................................7-3
7-2
Interrupt Controller Routing Scheme ........................................................................................................................7-4
7-3
GPIO/Generic MUX Cell .......................................................................................................................................7-24
7-4
Diagram—Suggested Crystal Oscillator Circuit .....................................................................................................7-65
8-1
Block Diagram—SDRAM Subsystem Example .....................................................................................................8-10
8-2
Block Diagram—SDRAM Memory Controller ......................................................................................................8-12
8-3
Address Bus Mapping .............................................................................................................................................8-25
9-1
LPC Concept Diagram ..............................................................................................................................................9-3
9-2
Muxed Mode Address Latching ................................................................................................................................9-3
9-3
Output Enable Signal .................................................................................................................................................9-4
9-4
Timing Diagram—Non-MUXed Mode .....................................................................................................................9-6
9-5
Timing Diagram - MUXed Mode .............................................................................................................................9-9
10-1
PCI Block Diagram .................................................................................................................................................10- 2
10-2
PCI Read Terminated by Master ...........................................................................................................................10-43
10-3
PCI Write Terminated by Target ...........................................................................................................................10-44
10-4
Contents of the AD Bus During Address Phase of a Type 0 Configuration Transaction .....................................10-47
10-5
Contents of the AD Bus During Address Phase of a Type 1 Configuration Transaction .....................................10-47
10-6
Initiator Arbitration Block Diagram ......................................................................................................................10-48
10-7
Type 0 Configuration Translation .........................................................................................................................10-52
10-8
Inbound Address Map ...........................................................................................................................................10-62
10-9
Outbound Address Map .........................................................................................................................................10-63
11-1
ATA Controller Interface ........................................................................................................................................11-1
11-2
Connections—Controller Cable, System Board, MPC5200 .................................................................................11-24
11-3
Pin Description—ATA Interface ...........................................................................................................................11-26
11-4
ATA Sector Format ...............................................................................................................................................11-29
11-5
Timing Diagram—PIO Read Command (Class 1) ...............................................................................................11-31
11-6
Timing Diagram—PIO Write Command (Class 2) ..............................................................................................11-32
11-7
Timing Diagram—Non-Data Command (Class 3) ...............................................................................................11-32
11-8
Flow Diagram—DMA Command Protocol ..........................................................................................................11-34
11-9
Timing Diagram—DMA Command (Class 4) ......................................................................................................11-35
11-10
Timing Diagram—Reset Timing ...........................................................................................................................11-37