Freescale Semiconductor MPC5200B - Manual (Page 22)

List of Figures
Figure Page
Number Number
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor LOF-3
19-11 Initialization Request/Acknowledge Cycle ...........................................................................................................19-35
20-1 BDLC Operating Modes State Diagram .................................................................................................................20-2
20-2 BDLC Block Diagram .............................................................................................................................................20-4
20-3 Types of In-Frame Response .................................................................................................................................20-10
20-4 J1850 Bus Message Format (VPW) ......................................................................................................................20-16
20-5 J1850 VPW Symbols .............................................................................................................................................20-18
20-6 J1850 VPW Passive Symbols ................................................................................................................................20-22
20-7 J1850 VPW EOF and IFS Symbols ......................................................................................................................20-23
20-8 J1850 VPW Active Symbols .................................................................................................................................20-24
20-9 J1850 VPW BREAK Symbol ................................................................................................................................20-24
20-10 J1850 VPW Bitwise Arbitrations ..........................................................................................................................20-25
20-11 BDLC Module Rx Digital Filter Block Diagram ..................................................................................................20-28
20-12 BDLC Protocol Handler Outline ...........................................................................................................................20-29
20-13 Basic BDLC Transmit Flowchart ..........................................................................................................................20-33
20-14 Basic BDLC Receive Flowchart ...........................................................................................................................20-36
20-15 Transmitting A Type 1 IFR ...................................................................................................................................20-40
20-16 Transmitting A Type 2 IFR ...................................................................................................................................20-41
20-17 Transmitting A Type 3 IFR ...................................................................................................................................20-43
20-18 Receiving An IFR With the BDLC module ..........................................................................................................20-45
20-19 Basic BDLC Module Transmit Flowchart ............................................................................................................20-47
20-20 Basic BDLC Module Initialization Flowchart ......................................................................................................20-50
21-1 Generic TLM/TAP Architecture Diagram ..............................................................................................................21-2
21-2 Generic TAP Link Module (TLM) Diagram ..........................................................................................................21-3
21-3 Generic Slave TAP ..................................................................................................................................................21-4
21-4 State Diagram—TAP Controller .............................................................................................................................21-6
21-5 G2_LE Core JTAG/COP Serial Interface ...............................................................................................................21-7
21-6 COP Connector Diagram .......................................................................................................................................21-11