Freescale Semiconductor MPC5200B User Manual
Page 25
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List of Tables
Table
Page
Number
Number
MPC5200B Users Guide, Rev. 1
LOT-2
Freescale Semiconductor
5-19
CDM PSC2 Mclock Config ....................................................................................................................................5-21
5-20
CDM PSC3 Mclock Config ....................................................................................................................................5-21
5-21
CDM PSC6 Mclock Config ....................................................................................................................................5-22
6-1
SVR Values ...............................................................................................................................................................6-1
7-1
Interrupt Sources .......................................................................................................................................................7-1
7-2
System Management Interrupt Pin Interrupts ...........................................................................................................7-2
7-3
Core Interrupt Pins Summary ....................................................................................................................................7-2
7-4
ICTL Peripheral Interrupt Mask Register .................................................................................................................7-5
7-5
ICTL Peripheral Priority and HI/LO Select 1 Register ............................................................................................7-7
7-6
ICTL Peripheral Priority and HI/LO Select 2 Register ............................................................................................7-8
7-7
ICTL Peripheral Priority and HI/LO Select 3 Register ............................................................................................7-8
7-8
ICTL External Enable and External Types Register .................................................................................................7-9
7-9
ICTL Critical Priority and Main Interrupt Mask Register) .....................................................................................7-10
7-10
ICTL Main Interrupt Priority and INT/SMI Select 1 Register ...............................................................................7-12
7-11
ICTL Main Interrupt Priority and INT/SMI Select 2 Register ...............................................................................7-13
7-12
ICTL PerStat, MainStat, CritStat Encoded Register ...............................................................................................7-14
7-13
ICTL Critical Interrupt Status All Register .............................................................................................................7-15
7-14
ICTL Main Interrupt Status All Register ................................................................................................................7-16
7-15
ICTL Peripheral Interrupt Status All Register ........................................................................................................7-17
7-16
ICTL Bus Error Status Register ..............................................................................................................................7-18
7-17
ICTL Main Interrupt Emulation All Register ..........................................................................................................7-19
7-18
ICTL Peripheral Interrupt Emulation All Register ..................................................................................................7-20
7-19
ICTL IRQ Interrupt Emulation All Register ...........................................................................................................7-21
7-20
GPIO Pin List ..........................................................................................................................................................7-22
7-21
GPS Port Configuration Register ............................................................................................................................7-28
7-22
GPS Simple GPIO Enables Register .......................................................................................................................7-31
7-23
GPS Simple GPIO Open Drain Type Register ........................................................................................................7-32
7-24
GPS Simple GPIO Data Direction Register ............................................................................................................7-33
7-25
GPS Simple GPIO Data Output Values Register ....................................................................................................7-36
7-26
GPS Simple GPIO Data Input Values Register .......................................................................................................7-37
7-27
GPS GPIO Output-Only Enables Register ..............................................................................................................7-38
7-28
GPS GPIO Output-Only Data Value Out Register .................................................................................................7-39
7-29
GPS GPIO Simple Interrupt Enables Register ........................................................................................................7-40
7-30
GPS GPIO Simple Interrupt Open-Drain Emulation Register ................................................................................7-40
7-31
GPS GPIO Simple Interrupt Data Direction Register .............................................................................................7-41
7-32
GPS GPIO Simple Interrupt Data Value Out Register ............................................................................................7-42
7-33
GPS GPIO Simple Interrupt Interrupt Enable Register ...........................................................................................7-42
7-34
GPS GPIO Simple Interrupt Interrupt Types Register ............................................................................................7-43
7-35
GPS GPIO Simple Interrupt Master Enable Register .............................................................................................7-44
7-36
GPS GPIO Simple Interrupt Status Register ...........................................................................................................7-44
7-37
GPW WakeUp GPIO Enables Register ...................................................................................................................7-46
7-38
GPW WakeUp GPIO Open Drain Emulation Register ...........................................................................................7-46
7-39
GPW WakeUp GPIO Data Direction Register ........................................................................................................7-47
7-40
GPW WakeUp GPIO Data Value Out Register ......................................................................................................7-48
7-41
GPW WakeUp GPIO Interrupt Enable Register .....................................................................................................7-48
7-42
GPW WakeUp GPIO Individual Interrupt Enable Register ....................................................................................7-49
7-43
GPW WakeUp GPIO Interrupt Types Register ......................................................................................................7-50
7-44
GPW WakeUp GPIO Master Enables Register ......................................................................................................7-51
7-45
GPW WakeUp GPIO Data Input Values Register ..................................................................................................7-52
7-46
GPW WakeUp GPIO Status Register .....................................................................................................................7-53
7-47
GPT 0 Enable and Mode Select Register ................................................................................................................7-55
7-48
GPT 0 Counter Input Register .................................................................................................................................7-58
7-49
GPT 0 PWM Configuration Register ......................................................................................................................7-59
7-50
GPT 0 Status Register .............................................................................................................................................7-60