Freescale Semiconductor MPC5200B - Manual (Page 21)

List of Figures
Figure Page
Number Number
MPC5200B Users Guide, Rev. 1
LOF-2 Freescale Semiconductor
12-2 Communication Channels .......................................................................................................................................12-2
12-3 Typical List Structure ..............................................................................................................................................12-3
12-3 Interrupt ED Structure .............................................................................................................................................12-4
12-4 Sample Interrupt Endpoint Schedule .......................................................................................................................12-5
13-1 Task Table .............................................................................................................................................................13-27
14-1 Block Diagram—FEC .............................................................................................................................................14-2
14-2 Ethernet Address Recognition - receive block decisions ......................................................................................14-39
14-3 Ethernet Address Recognition - microcode decisions ...........................................................................................14-40
15-1 PSC Functions Overview ........................................................................................................................................15-1
15-2 Simplified Block Diagram .......................................................................................................................................15-2
15-3 Signal configuration for a PSC/RS-232 interface .................................................................................................15-41
15-4 Clocking Source Diagram .....................................................................................................................................15-41
15-5 Timing Diagram—Transmitter ..............................................................................................................................15-42
15-6 Timing Diagram—Receiver ..................................................................................................................................15-43
15-7 PSC Codec Block Diagram ...................................................................................................................................15-45
15-8 PSC Codec Interface in Slave Mode .....................................................................................................................15-45
15-9 Clock Generation Diagram for Codec Mode ........................................................................................................15-46
15-10 Clock distribution network in cell phone mode ....................................................................................................15-48
15-11 SPI Parameter ........................................................................................................................................................15-49
15-12 Timing Diagram—16-Bit Codec Interface (lsb First, DTS1 = 0) .........................................................................15-50
15-13 Timing Diagram—8-Bit Codec Interface (msb First) ...........................................................................................15-50
15-14 I2S Data Transmission ..........................................................................................................................................15-55
15-15 PSC AC97 Block Diagram ....................................................................................................................................15-56
15-16 PSC - AC97 Interface ...........................................................................................................................................15-57
15-17 Timing Diagram—AC97 Interface .......................................................................................................................15-57
15-18 PSC SIR Block Diagram .......................................................................................................................................15-59
15-19 Data Format in SIR Mode .....................................................................................................................................15-59
15-20 PSC MIR and FIR Block Diagram ........................................................................................................................15-61
15-21 Serial Interaction Pulse (SIP) ................................................................................................................................15-62
15-22 Data Format in FIR Mode .....................................................................................................................................15-63
15-23 PSC FIFO System .................................................................................................................................................15-66
15-24 Automatic Echo .....................................................................................................................................................15-67
15-25 Local Loop-Back ...................................................................................................................................................15-68
15-26 Remote Loop-Back ................................................................................................................................................15-68
15-27 Timing Diagram—Multidrop Mode ......................................................................................................................15-69
16-1 Block Diagram of XLB Arbiter ...............................................................................................................................16-1
17-1 Block Diagram—SPI ...............................................................................................................................................17-2
18-1 Block Diagram—I 2 C Module .................................................................................................................................18-2
18-2 Timing Diagram—Start, Address Transfer and Stop Signal ...................................................................................18-3
18-3 Timing Diagram—Data Transfer ............................................................................................................................18-3
18-4 Timing Diagram—Receiver Acknowledgement .....................................................................................................18-4
18-5 Data Transfer, Combined Format ............................................................................................................................18-4
18-6 Timing Diagram—Clock Synchronization .............................................................................................................18-5
18-7 Timing Diagram—Arbitration Procedure ...............................................................................................................18-5
19-1 MSCAN Block Diagram .........................................................................................................................................19-1
19-2 The CAN System .....................................................................................................................................................19-3
19-3 User Model for Message Buffer Organization ......................................................................................................19-26
19-4 32-bit Maskable Identifier Acceptance Filter ........................................................................................................19-29
19-5 16-bit Maskable Identifier Acceptance Filters ......................................................................................................19-29
19-6 8-bit Maskable Identifier Acceptance Filters ........................................................................................................19-30
19-7 MSCAN Clocking Scheme ...................................................................................................................................19-31
19-8 Segments within the Bit Time ...............................................................................................................................19-32
19-9 Sleep Request / Acknowledge Cycle .....................................................................................................................19-34
19-10 Simplified State Transitions for Entering/Leaving Sleep Mode ...........................................................................19-35